Abstract: High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array having plural electrically erasable memory cells including a gate, a source, a drain, and an electric charge accumulation layer each disposed in a matrix form. A data writing section writes data into memory cells in this memory cell array. A data reading section reads out data in memory cells of the memory cell array. A data erasing section erases data in memory cells of the memory cell array. A control section controls, when applying a first signal to the gate in a specified memory inhibited of writing and applying a second signal to a node capacitively coupled to at least one of source and drain, in writing data into the memory cells, so that the second signal may fall later than the first signal.

Abstract: A memory cell in a NAND cell unit is constructed by a main transistor and parasitic transistor, which share a floating gate electrode and control gate electrode, and are connected in series with each other. The parasitic transistor is formed at an edge portion of the main transistor and, more particularly, an edge portion of the floating gate electrode. The threshold value of the parasitic transistor is higher than that of the main transistor. The parasitic transistor is formed in an offset area defined by the space between the edge portion of the floating gate electrode and the source/drain region. The offset area can be provided by forming a spacer on side wall portions of the floating gate electrode and control gate electrode.

Abstract: In the field of EEPROM, memory cell structures and operation methods have been required which are suitable for ultrahigh-integration and high-reliability EEPROMS with no danger of erroneous writing. To meet this requirement, in this invention, the gate of each of select gate cells located on the source line side and the bit line side of a NAND type memory cell array is formed of two layers of a charge storage layer and a control gate layer as with memory cells. The select gate cells are formed at the same time in the same process as memory cells. The ion implantation conditions for the cell channels are set so as to optimize the memory cell channel boost ratio. The optimization of the cutoff characteristic required of the select gate cells is performed by injection of charges into the charge storage layers of the select gate cells without owing to ion implantation. The memory and select gate cells are formed into the same shape. The charge storage layer is formed to self-align to an isolation trench.

Abstract: High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.

Abstract: An EEPROM includes a memory cell array section and a peripheral driving circuit section. The memory cell array section has memory cells which are arranged in a matrix form on a silicon substrate and each of which includes a floating gate coupled to the silicon substrate via a first capacitor having a first gate insulating film as a dielectric and a control gate coupled to the floating gate via a second capacitor having a second gate insulating film as a dielectric. In the outmost portion of the memory cell array section, memory cells of a first group are arranged and memory cells of a second group are arranged in the central portion on the inner side of the memory cell array section. The first gate insulating film of the first group of memory cells is thicker than the first gate insulating film of the second group of memory cells. The peripheral driving circuit section is formed adjacent to the memory cell array section on the silicon substrate.

Abstract: A method and system are provided for continuously maintaining replicas of an active database in a backup system for disaster recovery purposes. Redo records transmitted from an active system are received into a dataspace work area in a backup system memory. Redo records in the work area for an uncommitted database transaction are grouped together. When a transaction becomes a committed transaction, the redo records for the transaction are sorted with redo records from other committed transactions according to database, block number within a database, offset location within a block, and sequence of occurrence. A plurality of update blocks from a backup database are read into a buffer in the backup system memory. The sorted redo records are sequentially applied to corresponding data records in the update blocks. The update blocks are then immediately written back to the database.

Abstract: A method and system are provided for continuously maintaining replicas of an active database in a backup system for disaster recovery purposes. Redo records transmitted from an active system are received into a dataspace work area in a backup system memory. Redo records in the work area for an uncommitted database transaction are grouped together. When a transaction becomes a committed transaction, the redo records for the transaction are sorted with redo records from other committed transactions according to database, block number within a database, offset location within a block, and sequence of occurrence. A plurality of update blocks from a backup database are read into a buffer in the backup system memory. The sorted redo records are sequentially applied to corresponding data records in the update blocks. The update blocks are then immediately written back to the database.

Abstract: A controller which controls a refrigerating unit so that a temperature detected by a controlled temperature detector is equal to a setting temperature, includes a memory for storing the temperature detected by the detector, a card data input-output unit for reading data from a card and writing data in the card, a reading unit of the card data from the input-output unit, and a discriminator for discriminating whether the card is a setting card or a recording card on the basis of the card data read from the reading unit, whereby (a) when the discriminator discriminates that the card is the setting card, the setting temperature is set on the basis of the card data, and (b) when the discriminator discriminates that the card is the recording card, the temperature data stored in the memory is read to be written in the recording card through card data input-output unit, so that administration of data such as the setting temperature and the controlled temperature by a computer is attained and wrong setting of the tem