Abstract: An inscribed character is recognized with a device including a memory for storing signals representing the shapes of plural inscribed characters, a sensor for the shapes of inscribed characters, a comparator for the stored signals and signals from the sensor, and a display. The comparator compares a signal representing the sensed shape of the inscribed character and the stored signals representing the shapes of plural characters likely to be inscribed to derive signals representing plural selected candidate characters similar in shape to the inscribed character. In response to the signals representing plural selected candidate characters similar in shape to the inscribed character the plural candidate characters are displayed on a first region of the display abutting a second region where there is a representation of the inscribed character.

Abstract: A measuring device for measuring a glow center of a display device is provided with: an image pickup device which includes a sensing surface defined by a plurality of photoelectric conversion elements arranged in a two-dimensional manner at a specified pitch and picks up a light image to produce image data; an optical system which transmits a light image displayed on a display device to the sensing surface of the image pickup device; an optical system controller which controls the optical system to transmit the light image to the sensing surface in such a manner that the maximum spatial frequency of the light image at the sensing surface of the image pickup device is smaller than the reciprocal of the pitch of the photoelectric conversion element arrangement; and a calculator which calculates a glow center of the light image on the display device based on image data produced by the image pickup device.

Abstract: Even if various types of images exist together in an objective image, it is possible to sufficiently improve the quality of the image at all areas which are to be corrected. An image-correction apparatus has such a structure in which a CPU (10), an image-correction procedure part (12), a color monitor (14), a key board (16), a mouse (18), an inputting device (20), an image memory (22), an image-correction method memory (24), an outputting device (26) and the like are connected to a main bus (50). First, the CPU (10) instructs the inputting device (20) to read the objective image and store resultant data in the image memory (22), and instructs the color monitor (14) to display the objective image, using the image data which are stored. An operator then designate areas to be corrected, and selects a image-correction method which is suitable to the area from four types of image-correction methods, i.e.

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry.

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. The impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. The Y-select signal line overlaps the lower electrode layer of the capacitor element. A potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. The dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. The capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure.

Abstract: A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

Abstract: A CRT measurement device includes an image pickup device for producing an electrical image signal with respect to a light image displayed on the CRT, an optical system having a movable focusing lens for providing a light image of varied sharpness to the image pickup means in accordance with position of the focusing lens, a sharpness detector for detecting the sharpness of a picked up image based on an electrical image signal each time the focusing lens is moved, a focal position detector for detecting a focal position of the focusing lens providing a most sharpness light image, a driver for driving the focusing lens so as to move to the detected focal position, and calculator means for calculating a characteristic of the color CRT based on the image signal produced when the focusing lens is at the focal position. This device assures automatic and accurate focusing.

Abstract: There is provided an apparatus for predicting a tool life which reports a tool life ratio to an operator or a control device, when a remarkable change of work load values is detected. In a predicted life setting section 122, there is set a percentage of a quantity worked until the detection of the noticeable change of the work load values based on the workable quantity until the breakage of the tool which is regarded as 100%. A predicted residual work quantity calculating section 123 calculates a residual tool life value converted into a parameter at a point of time when an alarm is input from a work load monitoring section 121, on the basis of data of a work quantity accumulating section 120 and the predicted life setting section 122. A predicted residual work quantity outputting section 124 reports the residual tool life value to an operator or a control device.

Abstract: A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

Abstract: A light measurement device includes a photoelectric converter for receiving light from an object to be measured and converting the light to a measuring electrical energy in accordance with the intensity of the light, an offset amount measurement device for measuring the offset amount of the photoelectric converter, temperature measurement device for measuring a first temperature of the photoelectric converter when measuring the offset amount, and a second temperature of the photoelectric converter when measuring the light from the object, a memory device for storing a characteristic of the photoelectric converter with respect to temperature, correction amount calculation device for calculating a correction amount based on the characteristic, the first temperature, and the second temperature, and a light intensity calculation device for calculating a light intensity based on the measuring electrical energy, the offset amount, and the correction amount.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.

Abstract: Dynamic RAM having memory cells, each of the memory cells having a capacitor with the electrode comprised of a first semiconductor region of a first type of conductivity formed in a substrate of second conductivity type. The first semiconductor region is formed by introducing impurities using a mask comprising (1) a nitride film which is deposited so as to define part of the shape of the capacitor. An oxide film, formed by thermal oxidation of the substrate, defines the shape of the memory cells, and each of the memory cells further have at least a second semiconductor region of a second type of conductivity formed between and under the electrodes, the shape thereof being defined by the nitride film and the oxide film that is formed by thermal oxidation.

Abstract: A semiconductor integrated circuit device having first and second field-effect transistors, wherein the gate electrode of the first field-effect transistor is defined by a first-level conductor layer, while a wiring which is connected to the source or drain region of the first field-effect transistor is defined by a second-level conductor layer, and the gate electrode of the second field-effect transistor is defined by a combination of the first- and second-level conductor layers which are stacked one upon the other. Further, the respective gate electrodes of the first and second field-effect transistors are formed through respective gate insulator films which are formed on the principal surface of a semiconductor substrate in the same manufacturing step. By virtue of the above-described means, it is possible to reduce the area required for connection between the source or drain region of the first field-effect transistor and the wiring and to thereby increase the scale of integration of the device.

Abstract: A semiconductor memory device and a method of manufacturing the device wherein a field insulation is formed in a surface of a semiconductor body except for the source, drain and channel regions, a first floating gate is self-aligned to the channel region, a second gate insulated from the first floating gate covers the first floating gate and the first insulator having a width substantially same as the length of the channel region between the source and the drain regions.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: Dynamic RAM having memory cells, each of the memory cells having a capacitor with the electrode comprised of a first semiconductor region of a first type of conductivity formed in a substrate of second conductivity type. The first semiconductor region is formed by introducing impurities using a mask comprising (1) a nitride film which is deposited so as to define part of the shape of the capacitor. An oxide film, formed by thermal oxidation of the substrate, defines the shape of the memory cells, and each of the memory cells further have at least a second semiconductor region of a second type of conductivity formed between and under the electrodes, the shape thereof being defined by the nitride film and the oxide film that is formed by thermal oxidation.

Abstract: A semiconductor integrated circuit device having first and second field-effect transistors, wherein the gate electrode of the first field-effect transistor is defined by a first-level conductor layer, while a wiring which is connected to the source or drain region of the first field-effect transistor is defined by a second-level conductor layer, and the gate electrode of the second field-effect transistor is defined by a combination of the first- and second-level conductor layers which are stacked one upon the other. Further, the respective gate electrodes of the first and second field-effect transistors are formed through respective gate insulator films which are formed on the principal surface of a semiconductor substrate in the same manufacturing step. By virtue of the above-described means, it is possible to reduce the area required for connection between the source or drain region of the first field-effect transistor and the wiring and to thereby increase the scale of integration of the device.

Abstract: Disclosed are various semiconductor devices having vertical-type MISFETs wherein the source and drain regions of the MISFETs are spaced from each other in a direction perpendicular to the main surface of the semiconductor substrate containing such MISFETs. In a specific embodiment, a plurality of such MISFETs can be arrayed in a substrate, to form a memory device, with a common gate electrode, buried in the substrate, being used for a plurality of the memory cells, such buried gate electrode constituting the word line for the memory cells, with the data line extending over the surface of the substrate. This structure provides for increased miniaturization, without decrease in channel width of the MISFET, and provides for a flatter device surface due to the buried combination gate electrode/word lines.