Abstract: There is provided an apparatus for predicting a tool life which reports a tool life ratio to an operator or a control device, when a remarkable change of work load values is detected. In a predicted life setting section 122, there is set a percentage of a quantity worked until the detection of the noticeable change of the work load values based on the workable quantity until the breakage of the tool which is regarded as 100%. A predicted residual work quantity calculating section 123 calculates a residual tool life value converted into a parameter at a point of time when an alarm is input from a work load monitoring section 121, on the basis of data of a work quantity accumulating section 120 and the predicted life setting section 122. A predicted residual work quantity outputting section 124 reports the residual tool life value to an operator or a control device.

Abstract: A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

Abstract: A light measurement device includes a photoelectric converter for receiving light from an object to be measured and converting the light to a measuring electrical energy in accordance with the intensity of the light, an offset amount measurement device for measuring the offset amount of the photoelectric converter, temperature measurement device for measuring a first temperature of the photoelectric converter when measuring the offset amount, and a second temperature of the photoelectric converter when measuring the light from the object, a memory device for storing a characteristic of the photoelectric converter with respect to temperature, correction amount calculation device for calculating a correction amount based on the characteristic, the first temperature, and the second temperature, and a light intensity calculation device for calculating a light intensity based on the measuring electrical energy, the offset amount, and the correction amount.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.

Abstract: Dynamic RAM having memory cells, each of the memory cells having a capacitor with the electrode comprised of a first semiconductor region of a first type of conductivity formed in a substrate of second conductivity type. The first semiconductor region is formed by introducing impurities using a mask comprising (1) a nitride film which is deposited so as to define part of the shape of the capacitor. An oxide film, formed by thermal oxidation of the substrate, defines the shape of the memory cells, and each of the memory cells further have at least a second semiconductor region of a second type of conductivity formed between and under the electrodes, the shape thereof being defined by the nitride film and the oxide film that is formed by thermal oxidation.

Abstract: A semiconductor integrated circuit device having first and second field-effect transistors, wherein the gate electrode of the first field-effect transistor is defined by a first-level conductor layer, while a wiring which is connected to the source or drain region of the first field-effect transistor is defined by a second-level conductor layer, and the gate electrode of the second field-effect transistor is defined by a combination of the first- and second-level conductor layers which are stacked one upon the other. Further, the respective gate electrodes of the first and second field-effect transistors are formed through respective gate insulator films which are formed on the principal surface of a semiconductor substrate in the same manufacturing step. By virtue of the above-described means, it is possible to reduce the area required for connection between the source or drain region of the first field-effect transistor and the wiring and to thereby increase the scale of integration of the device.

Abstract: A semiconductor memory device and a method of manufacturing the device wherein a field insulation is formed in a surface of a semiconductor body except for the source, drain and channel regions, a first floating gate is self-aligned to the channel region, a second gate insulated from the first floating gate covers the first floating gate and the first insulator having a width substantially same as the length of the channel region between the source and the drain regions.

Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

Abstract: Dynamic RAM having memory cells, each of the memory cells having a capacitor with the electrode comprised of a first semiconductor region of a first type of conductivity formed in a substrate of second conductivity type. The first semiconductor region is formed by introducing impurities using a mask comprising (1) a nitride film which is deposited so as to define part of the shape of the capacitor. An oxide film, formed by thermal oxidation of the substrate, defines the shape of the memory cells, and each of the memory cells further have at least a second semiconductor region of a second type of conductivity formed between and under the electrodes, the shape thereof being defined by the nitride film and the oxide film that is formed by thermal oxidation.

Abstract: A semiconductor integrated circuit device having first and second field-effect transistors, wherein the gate electrode of the first field-effect transistor is defined by a first-level conductor layer, while a wiring which is connected to the source or drain region of the first field-effect transistor is defined by a second-level conductor layer, and the gate electrode of the second field-effect transistor is defined by a combination of the first- and second-level conductor layers which are stacked one upon the other. Further, the respective gate electrodes of the first and second field-effect transistors are formed through respective gate insulator films which are formed on the principal surface of a semiconductor substrate in the same manufacturing step. By virtue of the above-described means, it is possible to reduce the area required for connection between the source or drain region of the first field-effect transistor and the wiring and to thereby increase the scale of integration of the device.

Abstract: Disclosed are various semiconductor devices having vertical-type MISFETs wherein the source and drain regions of the MISFETs are spaced from each other in a direction perpendicular to the main surface of the semiconductor substrate containing such MISFETs. In a specific embodiment, a plurality of such MISFETs can be arrayed in a substrate, to form a memory device, with a common gate electrode, buried in the substrate, being used for a plurality of the memory cells, such buried gate electrode constituting the word line for the memory cells, with the data line extending over the surface of the substrate. This structure provides for increased miniaturization, without decrease in channel width of the MISFET, and provides for a flatter device surface due to the buried combination gate electrode/word lines.

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

Abstract: In a dynamic memory having a plurality of memory cells each of which consists of a MIS type field effect transistor and a charge storing capacitor connected thereto; a dynamic memory is disclosed wherein one electrode of the capacitor is made of a semiconductor layer which is formed on a semiconductor body through an insulating film and wherein a word line a part of which serves as a gate electrode of the MIS type field effect transistor is made of a conductor layer of multilayer structure which consists of a layer of semiconductor and a high-fusing metal layer containing the semiconductor.

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

Abstract: A semiconductor memory device includes a number of conductive layers for bit and selection lines alternately juxtaposed on the surface of a semiconductor substrate beneath a field insulating layer, with a number of MOS type memory cells arranged between the conductive layers for the bit and selection lines.

Abstract: A semiconductor memory device and a method of manufacturing the device wherein a field insulation is formed in a surface of a semiconductor body except for the source, drain and channel regions, a first floating gate is self-aligned to the channel region, a second gate insulated from the first floating gate covers the first floating gate and the first insulator having a width substantially same as the length of the channel region between the source and the drain regions.

Abstract: A metal-insulator semiconductor (MIS) device is manufactured by initially forming, on a semiconductor substrate, an insulating film having a hole therethrough and depositing silicon on the substrate to form a first monocrystalline silicon film in the hole and a polycrystalline silicon film on the insulating film. Then, a further insulating film is formed on the first silicon film, and a second silicon film is formed on the further insulating film. The second silicon film and the further insulating film are removed, so that the monocrystalline and polycrystalline parts of the first silicon film are exposed at both sides of the remaining part of the second silicon film and the further insulating film. Finally, an impurity is diffused to form a source and a drain region in the monocrystalline silicon film and conductive layers of polycrystalline silicon are disposed contiguous to the source and drain regions.

Abstract: A charge transfer semiconductor device includes charge transfer passages which are formed in the interior of a semiconductor substrate and between adjacent gate electrodes, so that when a control voltage is applied to the gate electrode, charges to be transferred are moved principally through the charge transfer passage, whereby the charges are prevented from being trapped between the gate electrodes.