Patents by Inventor Shinji Shirakawa

Shinji Shirakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240110594
    Abstract: A bearing device is configured to rotatably support a rotational shaft of a rotating machine and includes: a semi-floating bearing supported by a bearing housing; and an anti-rotation pin fixed to the bearing housing and having an insertion portion inserted from an outer peripheral side into an insertion hole formed on an outer surface of the semi-floating bearing. At least one of the insertion hole or the insertion portion has at least one protrusion that protrudes toward the other of the insertion hole or the insertion portion in a plan view perpendicular to an axis of the rotational shaft.
    Type: Application
    Filed: February 7, 2022
    Publication date: April 4, 2024
    Applicant: Mitsubishi Heavy Industries Marine Machinery & Equipment Co., Ltd.
    Inventors: Shinji Ogawa, Naoyuki Nagai, Takaya Futae, Taiyo Shirakawa
  • Patent number: 9948201
    Abstract: A module of conversion circuit includes a High side IGBT, a Low side IGBT connected in series to the High side IGBT, a first terminal connected to the High side IGBT, a second terminal connected to the Low side IGBT, a capacitor connected to the first terminal and the second terminal, and a third terminal connected to a connection point between the High side IGBT and the Low side IGBT. A fourth terminal is engaged with the first terminal. A fifth terminal is engaged with the second terminal. A sixth terminal is engaged with the third terminal. The first and second terminals have at portions thereof between front edges and rear edges high-resistance parts having higher resistance than other portions.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 17, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Shirakawa, Hiroshi Kamizuma, Daisuke Matsumoto, Akira Mima, Yukio Hattori
  • Publication number: 20160248337
    Abstract: A power conversion apparatus that is configured by a plurality of conversion circuit modules which are connected to each other in parallel, includes a first wiring that connects a positive electrode terminal of a first conversion circuit module among the conversion circuit modules, and a positive electrode side of a direct current wiring which supplies a direct current to the first conversion circuit module, and a second wiring that connects a negative electrode terminal of a second conversion circuit module which is different from the first conversion circuit module among the conversion circuit modules, and a negative electrode side of a direct current wiring which supplies a direct current to the second conversion circuit module, in which when a direct current flows to the power conversion apparatus, the first wiring and the second wiring are arranged such that a magnetic coupling is generated between the first wiring and the second wiring.
    Type: Application
    Filed: February 4, 2016
    Publication date: August 25, 2016
    Inventor: Shinji SHIRAKAWA
  • Publication number: 20160248338
    Abstract: A module of conversion circuit includes a High side IGBT, a Low side IGBT connected in series to the High side IGBT, a first terminal connected to the High side IGBT, a second terminal connected to the Low side IGBT, a capacitor connected to the first terminal and the second terminal, and a third terminal connected to a connection point between the High side IGBT and the Low side IGBT. A fourth terminal is engaged with the first terminal. A fifth terminal is engaged with the second terminal. A sixth terminal is engaged with the third terminal. The first and second terminals have at portions thereof between front edges and rear edges high-resistance parts having higher resistance than other portions.
    Type: Application
    Filed: February 22, 2016
    Publication date: August 25, 2016
    Inventors: Shinji SHIRAKAWA, Hiroshi KAMIZUMA, Daisuke MATSUMOTO, Akira MIMA, Yukio HATTORI
  • Publication number: 20140070314
    Abstract: There is provided an MOSFET having a large current density, which can be mixed with a logic circuit, and is used in a circuit that conducts the operation of applying a negative voltage to a drain electrode. An electrode surrounded by an insulating film is formed, at an intermediate position of a gate electrode and a drain of the MOSFET formed on an SOI substrate having a drain electrode applied with a negative voltage, and the electrode is connected to the ground to prevent a withstand voltage from being lowered which is caused by an increase in impurity concentration of a drift region. A drift resistance is lowered to improve the current density.
    Type: Application
    Filed: August 12, 2013
    Publication date: March 13, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Shinji Shirakawa, Junichi Sakano
  • Patent number: 8487343
    Abstract: A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: July 16, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Shirakawa, Junichi Sakano, Kenji Hara
  • Patent number: 8384124
    Abstract: The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: February 26, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Hara, Junichi Sakano, Shinji Shirakawa
  • Publication number: 20130001685
    Abstract: The present invention relates to an integrated circuit (semiconductor device) for which consolidation of a fine CMOS and a medium/high-voltage MOSFET is assumed to be carried out. A feature of the present invention is a small width (channel length) of a channel region CH. Specifically, when the width of the channel region planarly overlapped with a gate electrode is “L” and the thickness of the gate electrode is “t”, the channel region is formed to have the width of the channel region being larger than or equal to ? times the thickness t of the gate electrode and smaller than or equal to the thickness t. Thus, the width L of the channel region can be reduced, and variations in the threshold voltage can be reduced.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 3, 2013
    Applicant: Hitachi, Ltd.
    Inventors: Shinji SHIRAKAWA, Junichi SAKANO
  • Patent number: 7948058
    Abstract: A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: May 24, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Hara, Junichi Sakano, Shinji Shirakawa
  • Patent number: 7875509
    Abstract: In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm?3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: January 25, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Sakano, Kenji Hara, Shinji Shirakawa, Taiga Arai, Mutsuhiro Mori
  • Publication number: 20100327315
    Abstract: A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Inventors: Shinji SHIRAKAWA, Junichi Sakano, Kenji Hara
  • Publication number: 20100219448
    Abstract: The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.
    Type: Application
    Filed: February 18, 2010
    Publication date: September 2, 2010
    Inventors: Kenji HARA, Junichi Sakano, Shinji Shirakawa
  • Publication number: 20100165681
    Abstract: In a driving circuit, for controlling the turning on and off of a main semiconductor switching device of an insulated gate type, in an insulated gate semiconductor switching device for electric power conversion, bipolar semiconductor devices of an insulated gate control type, particularly insulated gate bipolar transistors (IGBTs) are used at the output stage of a circuit that controls the gate voltage of the main semiconductor switching device.
    Type: Application
    Filed: December 24, 2009
    Publication date: July 1, 2010
    Inventors: Junichi Sakano, Kenji Hara, Shinji Shirakawa
  • Publication number: 20090315072
    Abstract: In a lateral IGBT structure equipped with an emitter terminal, comprising two or more second conductivity type base layers, per one collector terminal, the second conductivity type base layer in the emitter region is covered by a first conductivity type layer which has a higher impurity concentration than the drift layer, and width L1 of the gate electrode located between two adjacent emitters is 4 ?m or less, or in addition to that, width L2 of the opening for leading out an emitter electrode located between two adjacent gate electrodes is 3 ?m or less.
    Type: Application
    Filed: June 18, 2009
    Publication date: December 24, 2009
    Applicant: Hitachi, Ltd.
    Inventors: Shinji Shirakawa, Junichi Sakano, Kenji Hara
  • Patent number: 7541758
    Abstract: V-phase upper-arm open phase detecting circuit outputs a permission signal to allow U-phase lower-arm MOSFET to be conductive when the V-phase voltage is higher than the positive electrode potential. In response to this permission signal, U-phase lower-arm driver circuit drives U-phase lower-arm MOSFET. V-phase lower-arm open phase detecting circuit outputs a permission signal to allow U-phase upper-arm MOSFET to be conductive when the V-phase voltage is lower than the negative electrode potential. In response to this permission signal, U-phase upper-arm driver circuit drives U-phase upper-arm MOSFET. Thereby, a MOS rectifying device capable of rectifying even when an open phase occurs, a driving method thereof, and a motor vehicle using thereof can be provided.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: June 2, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Masamitsu Inaba, Shinji Shirakawa, Masahiro Iwamura
  • Patent number: 7471004
    Abstract: An AC generator comprises a rotor and a stator having a three-phase winding. A three-phase inverter is connected to the three-phase winding. Here, the three-phase winding comprises at least two independent three-phase windings. Switching elements for respective phases of the three-phase inverter are connected in parallel by the number of the independent three-phase windings, and in-phase windings are individually connected to their parallel switching elements.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: December 30, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Kanazawa, Takashi Kobayashi, Noriaki Hino, Shinji Shirakawa, Keiichi Mashino, Masanori Tsuchiya
  • Patent number: 7453240
    Abstract: A generator having a field coil L, and an SW1 control circuit 2 for controlling field current flowing through the field coil L. When a generating operation of the generator is to be ended, a switch 1 SW1 is turned off to interrupt the field current flowing through the field coil L, and a switch 2 SW2 is turned off to allow the field current remaining the field coil L to the current path including a resistance element 1 with a resistance element capable of quickly attenuating the field current.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: November 18, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Tatsumi Yamauchi, Shinji Shirakawa, Masahiro Iwamura, Masamitsu Inaba, Keiichi Mashino, Keiji Kunii
  • Publication number: 20080265278
    Abstract: A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.
    Type: Application
    Filed: April 16, 2008
    Publication date: October 30, 2008
    Inventors: Kenji Hara, Junichi Sakano, Shinji Shirakawa
  • Publication number: 20080265331
    Abstract: In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm?3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.
    Type: Application
    Filed: April 16, 2008
    Publication date: October 30, 2008
    Inventors: Junichi Sakano, Kenji Hara, Shinji Shirakawa, Taiga Arai, Mutsuhiro Mori
  • Publication number: 20070200346
    Abstract: An AC generator comprises a rotor and a stator having a three-phase winding. A three-phase inverter is connected to the three-phase winding. Here, the three-phase winding comprises at least two independent three-phase windings. Switching elements for respective phases of the three-phase inverter are connected in parallel by the number of the independent three-phase windings, and in-phase windings are individually connected to their parallel switching elements.
    Type: Application
    Filed: May 7, 2007
    Publication date: August 30, 2007
    Applicant: Hitachi, Ltd.
    Inventors: Hiroshi Kanazawa, Takashi Kobayashi, Noriaki Hino, Shinji Shirakawa, Keiichi Mashino, Masanori Tsuchiya