Abstract: A module of conversion circuit includes a High side IGBT, a Low side IGBT connected in series to the High side IGBT, a first terminal connected to the High side IGBT, a second terminal connected to the Low side IGBT, a capacitor connected to the first terminal and the second terminal, and a third terminal connected to a connection point between the High side IGBT and the Low side IGBT. A fourth terminal is engaged with the first terminal. A fifth terminal is engaged with the second terminal. A sixth terminal is engaged with the third terminal. The first and second terminals have at portions thereof between front edges and rear edges high-resistance parts having higher resistance than other portions.

Abstract: A power conversion apparatus that is configured by a plurality of conversion circuit modules which are connected to each other in parallel, includes a first wiring that connects a positive electrode terminal of a first conversion circuit module among the conversion circuit modules, and a positive electrode side of a direct current wiring which supplies a direct current to the first conversion circuit module, and a second wiring that connects a negative electrode terminal of a second conversion circuit module which is different from the first conversion circuit module among the conversion circuit modules, and a negative electrode side of a direct current wiring which supplies a direct current to the second conversion circuit module, in which when a direct current flows to the power conversion apparatus, the first wiring and the second wiring are arranged such that a magnetic coupling is generated between the first wiring and the second wiring.

Abstract: A module of conversion circuit includes a High side IGBT, a Low side IGBT connected in series to the High side IGBT, a first terminal connected to the High side IGBT, a second terminal connected to the Low side IGBT, a capacitor connected to the first terminal and the second terminal, and a third terminal connected to a connection point between the High side IGBT and the Low side IGBT. A fourth terminal is engaged with the first terminal. A fifth terminal is engaged with the second terminal. A sixth terminal is engaged with the third terminal. The first and second terminals have at portions thereof between front edges and rear edges high-resistance parts having higher resistance than other portions.

Abstract: There is provided an MOSFET having a large current density, which can be mixed with a logic circuit, and is used in a circuit that conducts the operation of applying a negative voltage to a drain electrode. An electrode surrounded by an insulating film is formed, at an intermediate position of a gate electrode and a drain of the MOSFET formed on an SOI substrate having a drain electrode applied with a negative voltage, and the electrode is connected to the ground to prevent a withstand voltage from being lowered which is caused by an increase in impurity concentration of a drift region. A drift resistance is lowered to improve the current density.

Abstract: A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.

Abstract: The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.

Abstract: The present invention relates to an integrated circuit (semiconductor device) for which consolidation of a fine CMOS and a medium/high-voltage MOSFET is assumed to be carried out. A feature of the present invention is a small width (channel length) of a channel region CH. Specifically, when the width of the channel region planarly overlapped with a gate electrode is “L” and the thickness of the gate electrode is “t”, the channel region is formed to have the width of the channel region being larger than or equal to ? times the thickness t of the gate electrode and smaller than or equal to the thickness t. Thus, the width L of the channel region can be reduced, and variations in the threshold voltage can be reduced.

Abstract: A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.

Abstract: In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm?3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.

Abstract: A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.

Abstract: The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.

Abstract: In a driving circuit, for controlling the turning on and off of a main semiconductor switching device of an insulated gate type, in an insulated gate semiconductor switching device for electric power conversion, bipolar semiconductor devices of an insulated gate control type, particularly insulated gate bipolar transistors (IGBTs) are used at the output stage of a circuit that controls the gate voltage of the main semiconductor switching device.

Abstract: In a lateral IGBT structure equipped with an emitter terminal, comprising two or more second conductivity type base layers, per one collector terminal, the second conductivity type base layer in the emitter region is covered by a first conductivity type layer which has a higher impurity concentration than the drift layer, and width L1 of the gate electrode located between two adjacent emitters is 4 ?m or less, or in addition to that, width L2 of the opening for leading out an emitter electrode located between two adjacent gate electrodes is 3 ?m or less.

Abstract: V-phase upper-arm open phase detecting circuit outputs a permission signal to allow U-phase lower-arm MOSFET to be conductive when the V-phase voltage is higher than the positive electrode potential. In response to this permission signal, U-phase lower-arm driver circuit drives U-phase lower-arm MOSFET. V-phase lower-arm open phase detecting circuit outputs a permission signal to allow U-phase upper-arm MOSFET to be conductive when the V-phase voltage is lower than the negative electrode potential. In response to this permission signal, U-phase upper-arm driver circuit drives U-phase upper-arm MOSFET. Thereby, a MOS rectifying device capable of rectifying even when an open phase occurs, a driving method thereof, and a motor vehicle using thereof can be provided.

Abstract: An AC generator comprises a rotor and a stator having a three-phase winding. A three-phase inverter is connected to the three-phase winding. Here, the three-phase winding comprises at least two independent three-phase windings. Switching elements for respective phases of the three-phase inverter are connected in parallel by the number of the independent three-phase windings, and in-phase windings are individually connected to their parallel switching elements.

Abstract: A generator having a field coil L, and an SW1 control circuit 2 for controlling field current flowing through the field coil L. When a generating operation of the generator is to be ended, a switch 1 SW1 is turned off to interrupt the field current flowing through the field coil L, and a switch 2 SW2 is turned off to allow the field current remaining the field coil L to the current path including a resistance element 1 with a resistance element capable of quickly attenuating the field current.

Abstract: A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.

Abstract: In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm?3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.

Abstract: An AC generator comprises a rotor and a stator having a three-phase winding. A three-phase inverter is connected to the three-phase winding. Here, the three-phase winding comprises at least two independent three-phase windings. Switching elements for respective phases of the three-phase inverter are connected in parallel by the number of the independent three-phase windings, and in-phase windings are individually connected to their parallel switching elements.

Abstract: An inverter device is mounted on the rotating electric machine body The inverter device includes a module unit having a converter circuit and a control unit that controls the operation of the converter circuit. The converter circuit is configured by connecting a plurality of the following series circuits in parallel, each of the series circuits includes a P-channel MOS semiconductor device disposed at a higher potential side and an N-channel MOS semiconductor device disposed at a lower potential side which are electrically connected in series. An electric power that is supplied from a battery or an electric power that is supplied to the battery is controlled.