Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 ?m.

Abstract: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.

Abstract: A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 ?m.

Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.

Abstract: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.

Abstract: A distance between a contact and a gate electrode can be measured efficiently. Conversion data indicating a correlation between the distance between the first gate electrode and the first contact and a magnitude of a leakage current amount is prepared in advance. The leakage current amount between the first gate electrode and the first contact is measured, and the measured leakage current amount is converted into the distance between the first gate electrode and the first contact by using the conversion data. Then, a superposition error between an exposure process for forming the first gate electrode and an exposure process for forming the first contact can be measured from a difference between the measured value of the distance between the first gate electrode and the first contact and a design value of the distance.

Abstract: The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm?1 to 860 cm?1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.

Abstract: A wiring layout method includes designing a layout of a power wiring for an integrated circuit; designing a layout of plural signal wirings for the integrated circuit; comparing the signal frequency; classifying the signal wirings; calculating an evaluation value of a temperature rise; and modifying the layouts of the integrated circuit.

Abstract: An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product.

Abstract: A design method of a semiconductor device includes four steps. The first step is of arranging grid wiring which includes a plurality of wiring lines arranged in parallel to each other and a plurality of vias connecting the plurality of wiring lines with each other. The second step is of arranging a plurality of internal circuits connected to the grid wiring. The third step is of calculating a current density of a current flowing in the grid wiring by the plurality of internal circuits. The fourth step is of dividing each of the plurality of wiring lines into portions each having a wiring length such that electromigration corresponding to the current density is suppressed.

Abstract: Conventionally, an excessively strict current limitation is often adopted. An interconnection apparatus includes an acquisition unit and a decision unit. The acquisition unit serves to acquire a current density and data rate of a region that a specific interconnect passes through. The decision unit serves to decide whether the temperature increase corresponding to the current density and the data rate acquired by the acquisition unit is within a permissible range.

Abstract: A wiring layout method includes designing a layout of a power wiring for an integrated circuit; designing a layout of plural signal wirings for the integrated circuit; comparing the signal frequency; classifying the signal wirings; calculating an evaluation value of a temperature rise; and modifying the layouts of the integrated circuit. In the comparing the signal frequency, the signal frequency of each of the signal wirings is compared with a predetermined reference frequency. In the classifying the signal wirings, the signal wirings are classified into a first group in which a signal frequency is equal to or higher than a reference frequency and a second group in which a signal frequency is lower than the reference frequency. In the calculating an evaluation value of a temperature rise, an evaluation value of a temperature rise is calculated by excluding the temperature rise caused by a power consumption of the signal wirings of the first group.

Abstract: An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product.

Abstract: A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.

Abstract: The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration effectively. An input unit 101 stores interconnection information in an interconnection information storage unit 104. An arithmetic operation unit 102 acquires the interconnection information upon accessing the interconnection information storage unit 104 and acquires an arithmetic operation parameter while accessing the arithmetic operation parameter storage unit 105 to determine a width W of the interconnection based on these values. That is, the width W of the interconnection is made to determine upon multiplying (current i)1/3 by the arithmetic operation parameter (constant), which current is caused to flow through the interconnection.

Abstract: Conventionally, an excessively strict current limitation is often adopted. An interconnection apparatus includes an acquisition unit and a decision unit. The acquisition unit serves to acquire a current density and data rate of a region that a specific interconnect passes through. The decision unit serves to decide whether the temperature increase corresponding to the current density and the data rate acquired by the acquisition unit is within a permissible range.

Abstract: A slit portion is provided at the center of a shield common electrode which is overlapped with a drain wire as a different layer. When an interlayer short-circuiting occurs between the drain wire and the shield common electrode, it induces a critical defect on a screen display, however, a line defect can be repaired/extinguished by cutting both the sides of the slit at the short-circuited portion with laser repair and separating the short-circuited portion.

Abstract: The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration effectively. An input unit 101 stores interconnection information in an interconnection information storage unit 104. An arithmetic operation unit 102 acquires the interconnection information upon accessing the interconnection information storage unit 104 and acquires an arithmetic operation parameter while accessing the arithmetic operation parameter storage unit 105 to determine a width W of the interconnection based on these values. That is, the width W of the interconnection is made to determine upon multiplying (current i)1/3 by the arithmetic operation parameter (constant), which current is caused to flow through the interconnection.

Abstract: A slit portion is provided at the center of a shield common electrode which is overlapped with a drain wire as a different layer. When an interlayer short-circuiting occurs between the drain wire and the shield common electrode, it induces a critical defect on a screen display, however, a line defect can be repaired/extinguished by cutting both the sides of the slit at the short-circuited portion with laser repair and separating the short-circuited portion.

Abstract: An interconnect of a semiconductor device having a multilayer interconnect structure is designed by predicting the life of the interconnect governed by an electromigration with different predicting models that are classified according to a void incubation period and a void growth period of a void that occurs in the vicinity of a junction between the interconnect and a via which connects upper and lower interconnect, and designing the interconnect based on the predicted life. The different predicting models are classified according to whether the interconnect with the void is positioned above or below the via.