Abstract: A plurality of coaxial leads is made within a single via in a circuit substrate to enhance the density of vertical interconnection so as to match the demand for higher density multi-layers circuit interconnection between top circuit layer and bottom circuit layer of the substrate. Coaxial leads provide electromagnetic interference shielding among the plurality of coaxial leads in a single via.

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via.

Abstract: An ESD protection substrate is disclosed. The ESD protection substrate includes a first conductor, a second conductor, a pointed structure, and an ESD protection material. The pointed structure is electrically connected to the first or the second conductor. The ESD protection material is disposed between the first and the second conductors.

Abstract: A capacitor device is provided. The capacitor device includes at least one capacitor. The capacitor device also includes a first capacitor and a first filter coupling the first capacitor and a conductive region, wherein the first capacitor has a first resonance frequency and the first filter is configured to operate at a first frequency band covering the first resonance frequency.

Abstract: A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.

Abstract: A capacitive module is provided. The capacitive module may include a first capacitor including a first electrode and a second electrode, one of the first electrode and the second electrode being coupled to at least one first conductive via and the other one of the first electrode and the second electrode being coupled to at least one second conductive via. The capacitive module may also include a second capacitor spaced apart from the first capacitor, the second capacitor including a third electrode and a fourth electrode, one of the third electrode and the fourth electrode being coupled to the at least one first conductive via and the other one of the third electrode and the fourth electrode being coupled to the at least one second conductive via.

Abstract: An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.

Abstract: A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.

Abstract: A multi-tier capacitor structure has at least one multi-tier conductive layer. At least one conductive via passes through the multi-tier conductive layer. When currents flow through the conductive via, different current paths are presented in the conductive via in response to different current frequency; in other words, different inductor is induced. Therefore, a single plate capacitor structure has function of hierarchical decoupling capacitor effect.

Abstract: An electrically conductive structure includes a first conductive structure and a second conductive structure. Each has a conducting section at one end and a coupling section at the other end. The first and second conducting sections are electrically connected to a power and ground contact of an electronic device, respectively. The first and second coupling sections are respectively connected with power and ground layer of a circuit board. The first coupling sections are connected with the first conducting section through first extending sections and the second coupling sections are connected with the second conducting section through second extending sections. At least two coupling sections of the conductive structures are arranged in pairs. The first conductive structure and the second conductive structure are arranged in a staggered array to form two wiring loops having opposite current directions, thereby generating a magnetic flux cancellation effect.

Abstract: An ESD protection substrate is disclosed. The ESD protection substrate includes a first conductor, a second conductor, a pointed structure, and an ESD protection material. The pointed structure is electrically connected to the first or the second conductor. The ESD protection material is disposed between the first and the second conductors.

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via.

Abstract: A circuit board with embedded components includes a plurality of embedded components and at least one transmission line electrically connected to at least one of the embedded components and having a terminal circuit. Therefore, a measuring device is used to be electrically connected to the transmission line and send out a signal, so as to receive a corresponding reflected signal, and then, compare the received reflected signal with a signal pattern in the database to obtain an electrical parameter of the embedded component.

Abstract: A test method of an embedded capacitor and test system thereof are provided. The method and system are used to determine an electrical specification of the embedded capacitive component in a circuit board substrate, thereby avoiding executing a follow-up fabricating process for the circuit board substrate not satisfying the desired specification. In the method and system, a geometric size of the embedded capacitor is measured, and a relation value between the electrical parameter and the geometric size and a standard electrical parameter are obtained from a model database, to calculate the electrical parameter of the embedded capacitor. Then, the electrical parameter of the embedded capacitor is compared with the standard electrical parameter, to obtain an error value. Therefore, according to the error value, it may be acquired whether or not the circuit board substrate satisfies set electrical specifications.

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract: A test method of an embedded capacitor and test system thereof are provided. The method and system are used to determine an electrical specification of the embedded capacitive component in a circuit board substrate, thereby avoiding executing a follow-up fabricating process for the circuit board substrate not satisfying the desired specification. In the method and system, a geometric size of the embedded capacitor is measured, and a relation value between the electrical parameter and the geometric size and a standard electrical parameter are obtained from a model database, to calculate the electrical parameter of the embedded capacitor. Then, the electrical parameter of the embedded capacitor is compared with the standard electrical parameter, to obtain an error value. Therefore, according to the error value, it may be acquired whether or not the circuit board substrate satisfies set electrical specifications.