Patents by Inventor Shinn-Juh Lay
Shinn-Juh Lay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8174840Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.Type: GrantFiled: October 29, 2008Date of Patent: May 8, 2012Assignee: Industrial Technology Research InstituteInventors: Uei-Ming Jow, Chang-Sheng Chen, Chin-Sun Shyu, Min-Lin Lee, Shinn-Juh Lay, Ying-Jiunn Lai
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Patent number: 8035036Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.Type: GrantFiled: September 26, 2007Date of Patent: October 11, 2011Assignee: Industrial Technology Research InstituteInventors: Uei-Ming Jow, Min-Lin Lee, Shinn-Juh Lay, Chin-Sun Shyu, Chang-Sheng Chen, Ying-Jiunn Lai
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Patent number: 7893359Abstract: An embedded capacitor core including a first set of capacitors, a second set of capacitors, and an inter-layer dielectric film between the first set of capacitors and the second set of capacitors. The first set of capacitors includes: a first conductive pattern comprising at least two conductive electrodes; a second conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the first conductive pattern; and a first dielectric film between the first conductive pattern and the second conductive pattern. The second set of capacitors includes: a third conductive pattern comprising at least two conductive electrodes; a fourth conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the third conductive pattern; and a second dielectric film between the third conductive pattern and the fourth conductive pattern.Type: GrantFiled: September 6, 2006Date of Patent: February 22, 2011Assignee: Industrial Technology Research InstituteInventors: Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lay, Chih-Hao Chang
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Patent number: 7875808Abstract: An embedded capacitor device within a circuit board having an integrated circuitry thereon is provided. The circuit board has a common coupling area under the integrated circuitry. The embedded capacitor device includes a first capacitor section providing at least one capacitor to a first terminal set of the integrated circuitry and a second capacitor section providing at least one capacitor to a second terminal set of the integrated circuitry. A portion of the first capacitor section is in the common coupling area and has its coupling to the first terminal set located in the common coupling area. Similarly, a portion of the second capacitor section is in the common coupling area and has its coupling to the second terminal set located in the common coupling area.Type: GrantFiled: September 13, 2006Date of Patent: January 25, 2011Assignee: Industrial Technology Research InstituteInventors: Huey-Ru Chang, Min-Lin Lee, Shinn-Juh Lay, Chin Sun Shyu
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Patent number: 7714590Abstract: A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.Type: GrantFiled: February 20, 2007Date of Patent: May 11, 2010Assignee: Industrial Technology Research InstituteInventors: Uei-Ming Jow, Min-Lin Lee, Shinn-Juh Lay, Chin-Sun Shyu, Chang-Sheng Chen
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Patent number: 7515435Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.Type: GrantFiled: December 28, 2006Date of Patent: April 7, 2009Assignee: Industrial Technology Research InstituteInventors: Uei-Ming Jow, Chang-Sheng Chen, Chin-Sun Shyu, Min-Lin Lee, Shinn-Juh Lay, Ying-Jiunn Lai
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Publication number: 20090051469Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.Type: ApplicationFiled: October 29, 2008Publication date: February 26, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Uei-Ming Jow, Chang-Sheng Chen, Chin-Sun Shyu, Min-Lin Lee, Shinn-Juh Lay, Ying-Jiunn Lai
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Publication number: 20080093113Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.Type: ApplicationFiled: September 26, 2007Publication date: April 24, 2008Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Uei-Ming Jow, Min-Lin Lee, Shinn-Juh Lay, Chin-Sun Shyu, Chang-Sheng Chen, Ying-Jiunn Lai
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Patent number: 7349196Abstract: A composite distributed dielectric structure includes one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further formed around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers.Type: GrantFiled: June 17, 2005Date of Patent: March 25, 2008Assignee: Industrial Technology Research InstituteInventors: Chih-Hao Chang, Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lay
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Patent number: 7345366Abstract: A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.Type: GrantFiled: May 18, 2005Date of Patent: March 18, 2008Assignee: Industrial Technology Research InstituteInventors: Uei-Ming Jow, Min-Lin Lee, Shinn-Juh Lay, Chin-Sun Shyu, Chang-Sheng Chen
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Publication number: 20070164395Abstract: A chip package with built-in capacitor structure including an integrated circuit (IC) unit, a capacitor unit, a carrier and a molding compound is provided. The capacitor unit is disposed on the IC unit and includes a first metal foil, a second metal foil, and a dielectric layer disposed between the first metal foil and the second metal foil. The carrier is disposed on the surface away from the dielectric layer of the second metal foil. The first metal foil is electrically connected to the carrier, the second metal foil is electrically connected to the carrier, the IC unit is electrically connected to the carrier, the IC unit is electrically connected to the first metal foil, and the IC unit is electrically connected to the second metal foil. The molding compound is disposed on the carrier for fixing the IC unit, the capacitor unit and the carrier.Type: ApplicationFiled: March 30, 2006Publication date: July 19, 2007Inventors: Jiin-Shing Perng, Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lay
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Publication number: 20070164396Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.Type: ApplicationFiled: December 28, 2006Publication date: July 19, 2007Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Uei-Ming Jow, Chang-Sheng Chen, Chin-Sun Shyu, Min-Lin Lee, Shinn-Juh Lay, Ying-Jiunn Lai
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Publication number: 20070152339Abstract: A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.Type: ApplicationFiled: February 20, 2007Publication date: July 5, 2007Inventors: Uei-Ming Jow, Min-Lin Lee, Shinn-Juh Lay, Chin-Sun Shyu, Chang-Sheng Chen
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Publication number: 20070062725Abstract: An embedded capacitor core includes a first set of capacitors, a second set of capacitors, and an inter-layer dielectric film between the first set of capacitors and the second set of capacitors. The first set of capacitors includes: a first conductive pattern comprising at least two conductive electrodes; a second conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the first conductive pattern; and a first dielectric film between the first conductive pattern and the second conductive pattern. The second set of capacitors includes: a third conductive pattern comprising at least two conductive electrodes; a fourth conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the fourth conductive pattern; and a second dielectric film between the third conductive pattern and the fourth conductive pattern.Type: ApplicationFiled: September 6, 2006Publication date: March 22, 2007Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Shih-Hsien WU, Min-Lin LEE, Shinn-Juh LAY, Chi-Hao CHANG
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Publication number: 20070062726Abstract: An embedded capacitor device within a circuit board having an integrated circuitry thereon is provided. The circuit board has a common coupling area under the integrated circuitry. The embedded capacitor device includes a first capacitor section providing at least one capacitor to a first terminal set of the integrated circuitry and a second capacitor section providing at least one capacitor to a second terminal set of the integrated circuitry. A portion of the first capacitor section is in the common coupling area and has its coupling to the first terminal set located in the common coupling area. Similarly, a portion of the second capacitor section is in the common coupling area and has its coupling to the second terminal set located in the common coupling area.Type: ApplicationFiled: September 13, 2006Publication date: March 22, 2007Applicant: Industrial Technology Research InstituteInventors: Huey-Ru Chang, Min-Lin Lee, Shinn-Juh Lay, Chin Sun Shyu
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Publication number: 20060285273Abstract: This invention discloses a composite distributed dielectric structure. It comprises one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein, respectively described in two embodiments. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers The invention provides a low cost and practical dielectric structure for interconnect systems to reduce dielectric loss, cross talk, and signal propagation delay and to well control the impedance matching while maintaining proper heat dissipation and noise reduction at high frequency transmission.Type: ApplicationFiled: June 17, 2005Publication date: December 21, 2006Inventors: Chih-Hao Chang, Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lay
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Publication number: 20060261482Abstract: A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.Type: ApplicationFiled: May 18, 2005Publication date: November 23, 2006Inventors: Uei-Ming Jow, Min-Lin Lee, Shinn-Juh Lay, Chin-Sun Shyu, Chang-Sheng Chen
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Patent number: 7064427Abstract: A unitary buried array capacitor and microelectronic structures incorporating such capacitors are disclosed. A unitary buried array capacitor can be formed by a top layer of electrode, a middle layer of dielectric, and a bottom layer of electrode. A first electrode lead, a second electrode lead and at least one interconnect line pass through the three layers while only the first electrode lead making electrical contact with the top layer of electrode and only the second electrode lead making electrical contact with the bottom electrode.Type: GrantFiled: June 7, 2004Date of Patent: June 20, 2006Assignee: Industrial Technology Research InstituteInventors: Stephen Chung, Jungle Lee, Shinn-Juh Lay, Randy Wu, Huey-Ru Chang, Yu-Mei Cheng
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Publication number: 20050269685Abstract: A unitary buried array capacitor and microelectronic structures incorporating such capacitors are disclosed. A unitary buried array capacitor can be formed by a top layer of electrode, a middle layer of dielectric, and a bottom layer of electrode. A first electrode lead, a second electrode lead and at least one interconnect line pass through the three layers while only the first electrode lead making electrical contact with the top layer of electrode and only the second electrode lead making electrical contact with the bottom electrode.Type: ApplicationFiled: June 7, 2004Publication date: December 8, 2005Inventors: Stephen Chung, Jungle Lee, Shinn-Juh Lay, Randy Wu, Huey-Ru Chang, Yu-Mei Cheng
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Publication number: 20040211954Abstract: A compositive laminate substrate applicable for integrated and minimized electronic circuits is composed of at least an inorganic substrate and an organic substrate. The inorganic substrate is embedded with resistors, capacitors and inductors. Through the organic substrate (printed circuit boards), outer I/O ports are connected with the passive components of the inorganic substrate.Type: ApplicationFiled: July 16, 2003Publication date: October 28, 2004Inventors: Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lay