Abstract: A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.

Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Abstract: A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.

Abstract: A semiconductor memory device with a supply voltage generating circuit which can fine-tune its output voltages according to the frequency of a given clock signal. A reference voltage generator produces a plurality of different reference voltages. A clock signal receiver accepts a clock signal and supplies it to a period measurement unit for measurement of the cycle period of the given clock signal. A selector selects one of the produced reference voltages according to the clock period measured by the period measurement unit. A supply voltage generator produces a supply voltage corresponding to the selected reference voltage.

Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Abstract: A semiconductor memory device with a supply voltage generating circuit which can fine-tune its output voltages according to the frequency of a given clock signal. A reference voltage generator produces a plurality of different reference voltages. A clock signal receiver accepts a clock signal and supplies it to a period measurement unit for measurement of the cycle period of the given clock signal. A selector selects one of the produced reference voltages according to the clock period measured by the period measurement unit. A supply voltage generator produces a supply voltage corresponding to the selected reference voltage.

Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Abstract: A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.

Abstract: This invention provides an apparatus in which a time difference between an eternal clock signal and an internal clock signal is eliminated, and in which a high operation speed even at a high operation frequency is accomplished without causing erroneous circuit operations. A semiconductor integrated circuit device is equipped with a signal generator for generating an internal clock signal for determining an operation timing of an internal circuit from an external clock signal. The semiconductor integrated circuit device includes a delay unit for bringing an edge of the external clock signal into conformity with the edge of the internal clock signal by delaying the output of the signal generator by the time obtained by subtracting a time corresponding to a circuit delay of the signal generator from a time corresponding to some integral multiple of a 1/2 cycle of the external clock signal.

Abstract: A semiconductor memory device enabling change of the output organization has a plurality of memory cell array portions each having a plurality of memory cells for storing data, a plurality of data buses for transferring data, a plurality of sense amplifiers for sensing data of a selected memory cell of the memory cell array portions, and a plurality of output gates connected to the sense amplifiers. At least two of the sense amplifiers are connected to each of the memory cell array portions through the data buses, respectively. The selection of the sense amplifiers is controlled to be activated or deactivated by control signals, to thereby change the output organization. Therefore, a delay in data transmission can be eliminated, and a high speed operation can be realized.

Abstract: Additional transistors are serially inserted in a level conversion circuit that configures a flip-flop with N channel transistors and P channel transistors and that outputs TTL level output signals by converting ECL level input signals, so that said additional transistors are turned OFF at the same time as the P channel transistors, connected serially with the N channel transistors, are turned ON. This above described process will prevent a through current flowing between positive and negative power sources, when transistors are switched, thus preventing an increase in the current consumed.