Patents by Inventor Shinnosuke Kamata

Shinnosuke Kamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8717842
    Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takaaki Suzuki, Shinnosuke Kamata
  • Patent number: 8547776
    Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: October 1, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takaaki Suzuki, Shinnosuke Kamata
  • Publication number: 20130201751
    Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
    Type: Application
    Filed: August 31, 2012
    Publication date: August 8, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takaaki Suzuki, Shinnosuke Kamata
  • Patent number: 8077537
    Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Patent number: 8015389
    Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Patent number: 8004921
    Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: August 23, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Publication number: 20110141795
    Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
    Type: Application
    Filed: February 18, 2011
    Publication date: June 16, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yasurou MATSUZAKI, Takaaki SUZUKI, Masafumi YAMAZAKI, Kenichi KAWASAKI, Shinnosuke KAMATA, Ayako SATO, Masato MATSUMIYA
  • Patent number: 7911825
    Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 22, 2011
    Assignee: Fujitsu Semiconductor Ltd.
    Inventors: Yasurou Matsuzaki, Takaaki Suzuki, Masafumi Yamazaki, Kenichi Kawasaki, Shinnosuke Kamata, Ayako Sato, Masato Matsumiya
  • Patent number: 7814294
    Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: October 12, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Patent number: 7774577
    Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 10, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Publication number: 20100172200
    Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.
    Type: Application
    Filed: November 4, 2009
    Publication date: July 8, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Tomohiro KAWAKUBO, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Publication number: 20100146201
    Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.
    Type: Application
    Filed: November 4, 2009
    Publication date: June 10, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Patent number: 7729200
    Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: June 1, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Patent number: 7668040
    Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: February 23, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Publication number: 20090027988
    Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.
    Type: Application
    Filed: December 19, 2007
    Publication date: January 29, 2009
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Publication number: 20080189467
    Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
    Type: Application
    Filed: December 18, 2007
    Publication date: August 7, 2008
    Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Publication number: 20080181027
    Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.
    Type: Application
    Filed: December 19, 2007
    Publication date: July 31, 2008
    Inventors: Takahiro Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Publication number: 20080151678
    Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.
    Type: Application
    Filed: February 16, 2007
    Publication date: June 26, 2008
    Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Publication number: 20080151670
    Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.
    Type: Application
    Filed: February 23, 2007
    Publication date: June 26, 2008
    Inventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
  • Publication number: 20080151677
    Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.
    Type: Application
    Filed: January 26, 2007
    Publication date: June 26, 2008
    Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato