Patents by Inventor Shinnosuke Kamata
Shinnosuke Kamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8717842Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: GrantFiled: August 31, 2012Date of Patent: May 6, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Takaaki Suzuki, Shinnosuke Kamata
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Patent number: 8547776Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: GrantFiled: February 18, 2011Date of Patent: October 1, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Takaaki Suzuki, Shinnosuke Kamata
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Publication number: 20130201751Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: ApplicationFiled: August 31, 2012Publication date: August 8, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Takaaki Suzuki, Shinnosuke Kamata
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Patent number: 8077537Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: GrantFiled: November 4, 2009Date of Patent: December 13, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 8015389Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: GrantFiled: December 19, 2007Date of Patent: September 6, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 8004921Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: GrantFiled: November 4, 2009Date of Patent: August 23, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20110141795Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: ApplicationFiled: February 18, 2011Publication date: June 16, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yasurou MATSUZAKI, Takaaki SUZUKI, Masafumi YAMAZAKI, Kenichi KAWASAKI, Shinnosuke KAMATA, Ayako SATO, Masato MATSUMIYA
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Patent number: 7911825Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.Type: GrantFiled: August 30, 2006Date of Patent: March 22, 2011Assignee: Fujitsu Semiconductor Ltd.Inventors: Yasurou Matsuzaki, Takaaki Suzuki, Masafumi Yamazaki, Kenichi Kawasaki, Shinnosuke Kamata, Ayako Sato, Masato Matsumiya
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Patent number: 7814294Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: GrantFiled: January 26, 2007Date of Patent: October 12, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7774577Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: GrantFiled: December 19, 2007Date of Patent: August 10, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20100172200Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: November 4, 2009Publication date: July 8, 2010Applicant: FUJITSU LIMITEDInventors: Tomohiro KAWAKUBO, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20100146201Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: November 4, 2009Publication date: June 10, 2010Applicant: FUJITSU LIMITEDInventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7729200Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: GrantFiled: December 18, 2007Date of Patent: June 1, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Patent number: 7668040Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: GrantFiled: February 16, 2007Date of Patent: February 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20090027988Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: ApplicationFiled: December 19, 2007Publication date: January 29, 2009Applicant: Toyoda Gosei Co., Ltd.Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080189467Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: ApplicationFiled: December 18, 2007Publication date: August 7, 2008Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080181027Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: ApplicationFiled: December 19, 2007Publication date: July 31, 2008Inventors: Takahiro Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080151678Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.Type: ApplicationFiled: February 16, 2007Publication date: June 26, 2008Inventors: Hitoshi Ikeda, Takahiko Sato, Tatsuya Kanda, Toshiya Uchida, Hiroyuki Kobayashi, Satoru Shirakawa, Tetsuo Miyamoto, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080151670Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.Type: ApplicationFiled: February 23, 2007Publication date: June 26, 2008Inventors: Tomohiro Kawakubo, Syusaku Yamaguchi, Hitoshi Ikeda, Toshiya Uchida, Hiroyuki Kobayashi, Tatsuya Kanda, Yoshinobu Yamamoto, Satoru Shirakawa, Tetsuo Miyamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato
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Publication number: 20080151677Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.Type: ApplicationFiled: January 26, 2007Publication date: June 26, 2008Inventors: Takahiko Sato, Toshiya Uchida, Tatsuya Kanda, Tetsuo Miyamoto, Satoru Shirakawa, Yoshinobu Yamamoto, Tatsushi Otsuka, Hidenaga Takahashi, Masanori Kurita, Shinnosuke Kamata, Ayako Sato