Abstract: An OLT transmits and receives a CMTS/CM apparatus control signal through an apparatus physical management interface which is physically identical to or different from a main signal interface (NNI) and processes the CMTS apparatus control signal by itself. When connection of a new ONU is detected by an ONU apparatus control signal, an IP address is allocated by using the CM apparatus control signal in a manner similar to the CM. The CM apparatus control signal regarding the ONU is transmitted and received by using the IP address and a mutual conversion is performed between the CM apparatus control signal and the ONU apparatus control signal. The ONU processes the ONU apparatus control signal in a manner similar to the ONU based on an ordinary PON standard.

Abstract: An OLT transmits and receives a CMTS/CM apparatus control signal through an apparatus physical management interface which is physically identical to or different from a main signal interface (NNI) and processes the CMTS apparatus control signal by itself. When connection of a new ONU is detected by an ONU apparatus control signal, an IP address is allocated by using the CM apparatus control signal in a manner similar to the CM. The CM apparatus control signal regarding the ONU is transmitted and received by using the IP address and a mutual conversion is performed between the CM apparatus control signal and the ONU apparatus control signal. The ONU processes the ONU apparatus control signal in a manner similar to the ONU based on an ordinary PON standard.

Abstract: A passive optical network (PON) system which enables plural types of ONUs having different signal transmission speeds to be connected to one OLT. An optical line terminating apparatus (OLT) connected to plural types of ONUs having different signal transmission speeds through an optical distribution network includes an optical transmitter-receiver connected to the optical distribution network, a transmission/reception line interface connected to a wide area network, a downstream frame processing section for converting a packet received by the transmission/reception line interface from the wide area network into a downstream frame containing identification information on a destination ONU in a header, and a downstream transmission controller for modulating the downstream frame at a speed corresponding to a signal transmission speed of the destination ONU and outputting the modulated frame to an electrical/optical converter connected to the optical transmitter-receiver.

Abstract: An OLT transmits and receives a CMTS/CM apparatus control signal through an apparatus physical management interface which is physically identical to or different fro a main signal interface (NNI) and processes the CMTS apparatus control signal by itself. When connection of a new ONU is detected by an ONU apparatus control signal, an IP address is allocated by using the CM apparatus control signal in a manner similar to the CM. The CM apparatus control signal regarding the ONU is transmitted and received by using the IP address and a mutual conversion is performed between the CM apparatus control signal and the ONU apparatus control signal. The ONU processes the ONU apparatus control signal in a manner similar to the ONU based on an ordinary PON standard.

Abstract: An OLT transmits and receives a CMTS/CM apparatus control signal through an apparatus physical management interface which is physically identical to or different from a main signal interface (NNI) and processes the CMTS apparatus control signal by itself. When connection of a new ONU is detected by an ONU apparatus control signal, an IP address is allocated by using the CM apparatus control signal in a manner similar to the CM. The CM apparatus control signal regarding the ONU is transmitted and received by using the IP address and a mutual conversion is performed between the CM apparatus control signal and the ONU apparatus control signal. The ONU processes the ONU apparatus control signal in a manner similar to the ONU based on an ordinary PON standard.

Abstract: A passive optical network (PON) system which enables plural types of ONUs having different signal transmission speeds to be connected to one OLT. An optical line terminating apparatus (OLT) connected to plural types of ONUs having different signal transmission speeds through an optical distribution network includes an optical transmitter-receiver connected to the optical distribution network, a transmission/reception line interface connected to a wide area network, a downstream frame processing section for converting a packet received by the transmission/reception line interface from the wide area network into a downstream frame containing identification information on a destination ONU in a header, and a downstream transmission controller for modulating the downstream frame at a speed corresponding to a signal transmission speed of the destination ONU and outputting the modulated frame to an electrical/optical converter connected to the optical transmitter-receiver.

Abstract: A packet switching system including at least one switching node or local unit each including a label conversion unit for accommodating a plurality of packet circuits and performing conversion into output port information of a switch based on a logic channel on a packet circuit, a self-routing switch for performing switching based on the output port information, and a control unit for terminating a control packet and performing the call processing function. A switching node or tandem unit is provided including at least one self-routing switch for interconnecting the local units. A device is provided for setting, between the tandem unit and a destination-side local unit, the same logic channel as that between an originating-side local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than this local unit and a device.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Abstract: In a packet switching system-made up of a single or a plurality of switching nodes or local units each including a label conversion unit for accommodating a plurality of packet circuits and performing conversion into output port information of a switch on the basis of a logic channel on a packet circuit, a self-routing switch for performing switching on the basis of the output port information, and a control unit for terminating a control packet and performing the call processing function, and a switching node or tandem unit including a single or a plurality of self-routing switches for interconnecting the local units, there are provided a device for setting, between the tandem unit and a destination-side local unit, the same logic channel as that between an originating, side local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than this local unit and a device, operable in the originating-side local unit for information transfer, for inserting

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system including a switch unit having a plurality of input ports and output ports, and a multiplexer for multiplexing cell trains from at least two output ports into a single cell train and outputting the cell train to and output port. A demultiplexer can be provided in place of the multiplexer. The switch unit includes a buffer memory for storing cells from the input ports while forming a queue chain for each output port, a demultiplexer for distributing the cells from the buffer memory to output ports, and a buffer memory control circuit for controlling write and read operations of the buffer memory. The buffer memory control circuit has a control table for outputting an identifier of an output port the cells read from the buffer memory are to be output. Cells are read from the chain designated by the identifier.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: A packet switching system including at least one switching node or local unit each including a label conversion unit for accommodating a plurality of packet circuits and performing conversion into output port information of a switch based on a logic channel on a packet circuit, a self-routing switch for performing switching based on the output port information, and a control unit for terminating a control packet and performing the call processing function. A switching node or tandem unit is provided including at least one self-routing switch for interconnecting the local units. A device is provided for setting, between the tandem unit and a destination-side local unit, the same logic channel as that between an originating-side local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than this local unit and a device.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.