Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: In a packet switching system made up of a single or a plurality of switching nodes or local units each including a label conversion unit for accommodating a plurality of packet circuits and performing conversion into output port information of a switch on the basis of a logic channel on a packet circuit, a self-routing switch for performing switching on the basis of the output port information, land a control unit for terminating a control packet and performing the call processing function, and a switching node or tandem unit including a single or a plurality of self-routing switches for interconnecting the local units, there are provided a device for setting, between the tandem unit and a destination-side local unit, the same logic channel as that between an originating-side local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than this local unit and a device, operable in the originating side local unit for information transfer, for inserting

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: In a packet switching system made up of a single or a plurality of switching nodes or local units each including a label conversion unit for accommodating a plurality of packet circuits and performing conversion into output port information of a switch on the basis of a logic channel on a packet circuit, a self-routing switch for performing switching on the basis of the output port information, and a control unit for terminating a control packet and performing the call processing function, and a switching node or tandem unit including a single or a plurality of self-routing switches for interconnecting the local units, there are provided a device for setting, between the tandem unit and a destination-side local unit, the same logic channel as that between an originating, side local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than this local unit and a device, operable in the originating-side local unit for information transfer, for inserting

Abstract: A packet switching system which includes a device for setting, between a tandem unit and a destination local unit, the same logic channel as that between an originating local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than the originating local unit and a device, operable in the originating-side local unit for information transfer, for inserting output port information of a self-routing switch inside the tandem unit into a packet destined for the local unit other than this local unit; in the tandem unit, setting of logic channel conversion information is not required to be done and even when any control signal packet from the originating local unit arrives at the tandem unit, the packet is transferred to the destination local unit without undergoing termination of packet and concomitant call processing control.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Abstract: An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

Abstract: An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.

Abstract: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Abstract: A packet switching system which includes a device for setting, between a tandem unit and a destination local unit, the same logic channel as that between an originating local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than the originating local unit and a device, operable in the originating-side local unit for information transfer, for inserting output port information of a self-routing switch inside the tandem unit into a packet destined for the local unit other than this local unit. In the tandem unit, setting of logic channel conversion information is not required to be done and even when any control signal packet from the originating local unit arrives at the tandem unit, the packet is transferred to the destination local unit without undergoing termination of packet and concomitant call processing control.

Abstract: A switching system for handling a plurality of cells, each cell including a header section and a data section, and for exchanging a communication message contained in the data section of the cell between a plurality of incoming highways and a plurality of outgoing highways according to the data contained in the header section of the cell. The switching system includes a unit for multiplexing the incoming highways in time division, a first memory having addressable storage locations for storing cells received from the multiplexing unit, a unit for demultiplexing and distributing data output from the first memory among a plurality of outgoing highways, a second memory for storing an empty address of an empty storage location of the first memory, a unit for controlling the write and read operations of the first memory in accordance with an empty address stored in the second memory used as write and read addresses, and a unit for detecting an error in at least one of the write address and read address.

Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.