Patents by Inventor Shinpei Iijima

Shinpei Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060086961
    Abstract: A capacitor formed in a deep-hole has a bottom electrode, a capacitor insulator film and a top electrode. The bottom electrode includes a sidewall conductive film formed on the sidewall of a top portion of the deep-hole, and an inner conductive film formed on the sidewall conductive film and the sidewall and bottom of the through-hole. The inner conductive film is in contact with the underlying contact plug.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 27, 2006
    Applicant: Elpida Memory, Inc.
    Inventors: Shinpei Iijima, Keiji Kuroki
  • Patent number: 6927439
    Abstract: A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: August 9, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hiroyuki Ohta, Shinpei Iijima, Isamu Asano, Yuzuru Ohji, Yoshitaka Nakamura
  • Publication number: 20050118762
    Abstract: After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.
    Type: Application
    Filed: November 30, 2004
    Publication date: June 2, 2005
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoshitaka Nakamura, Tsuyoshi Kawagoe, Hiroshi Sakuma, Isamu Asano, Keiji Kuroki, Hidekazu Goto, Shinpei Iijima
  • Publication number: 20050024811
    Abstract: A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
    Type: Application
    Filed: August 23, 2004
    Publication date: February 3, 2005
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hiroyuki Ohta, Shinpei Iijima, Isamu Asano, Yuzuru Ohji, Yoshitaka Nakamura
  • Publication number: 20040227175
    Abstract: A lower electrode of a capacitor element is formed by manufacturing a crown structure while using a first conducting material such as titanium nitride or the like excellent in mechanical strength as a base material and by forming a film of a second conducting material such as ruthenium or the like, which is comparatively difficult to be oxidized, on a surface of the crown structure. First, ruthenium is deposited on a surface of the crown structure by using a sputtering method. Thereafter, the ruthenium (sputtered ruthenium) placed in a peripheral region of the crown structure is removed by etching, and a film of ruthenium is further formed on a surface of the crown structure by using a CVD method while using the sputtered ruthenium as a seed layer.
    Type: Application
    Filed: March 16, 2004
    Publication date: November 18, 2004
    Inventors: Shinpei Iijima, Keiji Kuroki
  • Publication number: 20040171241
    Abstract: A semiconductor device has a reduced contact resistance between a tungsten film and a polysilicon layer and has a gate electrode prevented from being depleted for a reduced gate resistance. According to a method of fabricating such a semiconductor device, a semiconductor device having a gate electrode of a polymetal gate structure which comprises a three-layer structure having a tungsten (W) film, a tungsten nitride (WN) film, and a polysilicon (PolySi) layer, is manufactured by nitriding the sides of the gate electrode at a nitriding temperature ranging from 700° C. to 950° C. in an ammonia atmosphere after the gate electrode is formed and before side selective oxidization is performed on the gate electrode.
    Type: Application
    Filed: January 14, 2004
    Publication date: September 2, 2004
    Inventors: Eiji Kitamura, Satoru Yamada, Yoshiki Kato, Kanta Saino, Masayoshi Saito, Shinpei Iijima, Kiyonori Oyu
  • Patent number: 6781172
    Abstract: A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Moriya, Tomio Iwasaki, Hiroyuki Ohta, Shinpei Iijima, Isamu Asano, Yuzuru Ohji, Yoshitaka Nakamura
  • Patent number: 6724034
    Abstract: In a semiconductor integrated circuit device, a polycrystalline silicon film is formed along an inner wall of a trench in which a capacitor is to be formed, and the polycrystalline silicon film and a lower electrode is contacted to each other on the entire inner wall of the trench. Oxygen permeated into the lower electrode during a thermal treatment of a tantalum oxide film is consumed at an interface between the polycrystalline silicon film and the lower electrode. Thus, oxygen does not reach the surface of a silicon plug below the lower electrode that would cause oxidation on the surface of the silicon plug and form a high-resistance oxide layer when a dielectric film formed on a lower electrode of a capacitor of a DRAM is subjected to a thermal treatment in an oxygen atmosphere.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: April 20, 2004
    Assignees: Renesas Technology Corporation, NEC Corporation, NEC Electronics Corporation
    Inventors: Shinpei Iijima, Hiroshi Sakuma
  • Patent number: 6723612
    Abstract: In a semiconductor integrated circuit device, a polycrystalline silicon film is formed along an inner wall of a trench in which a capacitor is to be formed, and the polycrystalline silicon film and a lower electrode are contacted to each other on the entire inner wall of the trench. Oxygen permeated into the lower electrode during a thermal treatment of a tantalum oxide film is consumed at an interface between the polycrystalline silicon film and the lower electrode. Thus, oxygen does not reach the surface of a silicon plug below the lower electrode that would cause oxidation on the surface of the silicon plug and form a high-resistance oxide layer when a dielectric film formed on a lower electrode of a capacitor of a DRAM is subjected to a thermal treatment in an oxygen atmosphere.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: April 20, 2004
    Assignees: Renesas Technology Corproation, NEC Corporation, NEC Electronics Corporation
    Inventors: Shinpei Iijima, Hiroshi Sakuma
  • Patent number: 6720603
    Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: April 13, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Yuzuru Ohji, Masato Kunitomo, Masahiko Hiratani, Yuichi Matsui, Hiroyuki Ohta, Yukihiro Kumagai
  • Patent number: 6713343
    Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Sugawara, Shinpei Iijima, Yuzuru Oji, Naruhiko Nakanishi, Misuzu Kanai, Masahiko Hiratani
  • Patent number: 6664157
    Abstract: Plug electrodes of silicon are formed so as to be buried in through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes a dielectric is formed to form lower electrodes of the capacitor elements and an upper electrode therefor.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: December 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Yoshitaka Nakamura, Masahiko Hiratani, Yuichi Matsui, Naruhiko Nakanishi
  • Publication number: 20030224571
    Abstract: A semiconductor integrated circuit device includes a plurality of capacitor elements, which are separated from each other by a first insulating film on a plane. Each of the plurality of capacitor elements has a lower electrode, a dielectric film, and an upper electrode, and the lower electrode has a crown structure. At least one of the lower electrode and the upper electrode has a laminate structure composed of a plurality of conductive films. An outermost film of the laminate structure on a side of the dielectric film is a ruthenium film, and a portion of the laminate structure other than the outermost film has higher selective growth than the first insulating film with respect to the ruthenium film. Here, the first insulating film is desirably a tantalum oxide film.
    Type: Application
    Filed: May 22, 2003
    Publication date: December 4, 2003
    Inventors: Shinpei Iijima, Hiroshi Sakuma
  • Patent number: 6653676
    Abstract: The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: November 25, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Tsu, Isamu Asano, Shinpei Iijima, William R. McKee
  • Patent number: 6649465
    Abstract: A technique is provided which is capable of forming a Ru film constituting a lower electrode of an information storing capacitive element in an aperture with high precision. After a Ru film is deposited, heat treatment is performed in a reducing atmosphere on a side wall and a bottom portion of a deep aperture in which the information storing capacitive element is formed. The deposition and heating of Ru films can be repeated to form a laminated structure of Ru films. As a result, it is possible to effectively remove impurities included in the Ru film, and to achieve fineness of the Ru film.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: November 18, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Satoshi Yamamoto
  • Patent number: 6632721
    Abstract: In a method of manufacturing a semiconductor integrated circuit device in which a lower electrode of a capacitor is composed of a polycrystalline silicon film having a surface area increased by surface roughening, an impurity is introduced into the polycrystalline silicon film by vapor phase diffusion in order to reduce the resistance of the lower electrode.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: October 14, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinpei Iijima, Satoshi Yamamoto, Jun Kuroda, Hiroshi Miki, Yoshihisa Fujisaki, Tadanori Yoshida, Kenichi Yamaguchi
  • Publication number: 20030173614
    Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of improving the characteristics of the semiconductor integrated circuit device by reducing a leakage current of a capacitor used in a DRAM memory cell. A data storage capacitor connected to a data transfer MISFET in a memory cell forming area via plugs is formed in the following manner. That is, a lower electrode composed of an Ru film is formed in a hole in a silicon oxide film, and then, a tantalum oxide film is deposited on the lower electrode. Thereafter, a first thermal treatment in an oxidizing atmosphere is performed to the film at a temperature sufficient to repair an oxygen defect and having no influence on the materials below the tantalum oxide film. Further, a second thermal treatment in an inactive atmosphere is performed at a temperature at which the tantalum oxide film is not completely crystallized (650° C.) and higher than that applied in the later process.
    Type: Application
    Filed: January 28, 2003
    Publication date: September 18, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Isamu Asano, Shinpei Iijima, Masahiko Hiratani, Hiroshi Sakuma
  • Publication number: 20030162357
    Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.
    Type: Application
    Filed: March 17, 2003
    Publication date: August 28, 2003
    Inventors: Yasuhiro Sugawara, Shinpei Iijima, Yuzuru Oji, Naruhiko Nakanishi, Misuzu Kanai
  • Publication number: 20030141533
    Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of improving the characteristics of the semiconductor integrated circuit device by reducing a leakage current of a capacitor used in a DRAM memory cell. A data storage capacitor connected to a data transfer MISFET in a memory cell forming area via plugs is formed in the following manner. That is, a lower electrode composed of an Ru film is formed in a hole in a silicon oxide film, and then, a tantalum oxide film is deposited on the lower electrode. Thereafter, a first thermal treatment in an oxidizing atmosphere is performed to the film at a temperature sufficient to repair an oxygen defect and having no influence on the materials below the tantalum oxide film. Further, a second thermal treatment in an inactive atmosphere is performed at a temperature at which the tantalum oxide film is not completely crystallized (650° C.) and higher than that applied in the later process.
    Type: Application
    Filed: January 28, 2003
    Publication date: July 31, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yoshitaka Nakamura, Isamu Asano, Shinpei Iijima, Masahiko Hiratani, Hiroshi Sakuma
  • Publication number: 20030132462
    Abstract: In a semiconductor integrated circuit device according to the present invention, a polycrystalline silicon film is formed along an inner wall of a trench in which a capacitor is to be formed, and the polycrystalline silicon film and a lower electrode is contacted to each other on the entire inner wall of the trench. Therefore, oxygen permeated into the lower electrode at the time of a thermal treatment of a tantalum oxide film is consumed at an interface between the polycrystalline silicon film and the lower electrode. Thus, the oxygen does not reach the surface of the plug, so that such a disadvantage can be prevented that the oxygen permeated through the lower electrode causes the oxidation on the surface of the silicon plug below the lower electrode to form a high-resistance oxide layer when a dielectric film formed on a lower electrode of a capacitor of a DRAM is subjected to a thermal treatment in an oxygen atmosphere.
    Type: Application
    Filed: January 30, 2003
    Publication date: July 17, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Shinpei Iijima, Hiroshi Sakuma