Patents by Inventor Shinpei Iijima

Shinpei Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having an arrangement of IGFETs and capacitors stacked thereover
    Patent number: 5091761
    Abstract: Disclosed is a semiconductor device including a charge storage capacitor having a storage electrode which is electrically connected to a switching transistor through a contact hole provided in an insulator and which has a greater film thickness than the radius of the contact hole, at least a part of the storage electrode being disposed above a data line. It is possible to reduce the memory cell area while preventing lowering in the capacitance, and thus realize high density and high integration of semiconductor devices.
    Type: Grant
    Filed: July 25, 1989
    Date of Patent: February 25, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Hiraiwa, Shinichiro Kimura, Toshiyuki Mine, Takashi Kobayashi, Tokuo Kure, Shinpei Iijima, Jiro Yugami
  • Semiconductor capacitor
    Patent number: 4989056
    Abstract: A capacitor having a first electrode, a thin insulator formed on said first electrode and a second electrode formed on said insulator wherein said first and second electrodes are composed of semiconductors that are of complementary conductivity type. Therefore, the current that flows through the capacitor insulator is efficiently suppressed while the thickness of the insulator is decreased, making it possible to realize a capacitor of a small area yet having a large capacitance.
    Type: Grant
    Filed: May 10, 1989
    Date of Patent: January 29, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Hiraiwa, Shinpei Iijima, Jiro Yugami
  • Static random access memory having structure of first-, second- and third-level conductive films
    Patent number: 4785342
    Abstract: A resistance element having a reduced occupied area and a high resistance which may be employed as a load resistor used in, for example, a static memory device. A high-resistance area is formed using a relatively thin film, while an interconnection area is formed using a relatively thick film, and these films are provided in such a manner that the thin film is in contact with the upper side of the thick film (the relatively thick film is a first-level film, and the relatively thin film is a second-level film).
    Type: Grant
    Filed: January 29, 1987
    Date of Patent: November 15, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Yamanaka, Yoshio Sakai, Shinpei Iijima, Osamu Minato, Shigeru Honjyo