Patents by Inventor Shintaro Nakano

Shintaro Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170263681
    Abstract: According to one embodiment, a semiconductor memory device includes first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction, a first semiconductor layer extending in the second direction and including a material having one of a first conductivity type and a second conductivity type, a first insulation layer disposed inside the first semiconductor layer, a second conductive layer disposed inside the first insulation layer, and a variable resistance layer disposed between the first conductive layers and the first semiconductor layer.
    Type: Application
    Filed: March 10, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shuichi TORIYAMA, Kenichi MUROOKA, Shintaro Nakano, Tatsuya OHGURO
  • Patent number: 9759272
    Abstract: A clutch is provided with a drive-side rotational body and a driven-side rotational body, which can move in the axial direction between a coupled position and a decoupled position. The driven-side rotational body has a groove having a helical portion and an annular portion that is deeper than the helical portion. The driven-side rotational body is urged toward the coupled position by an urging member. The driven-side rotational body is moved to the decoupled position against the urging force of the urging member by insertion of a pin into the helical portion. A projection is provided on the tip of the pin, and a recessed groove for accommodating the projection when the pin is inserted into the helical portion is provided in the bottom surface of the helical portion.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: September 12, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirotaka Sunada, Masao Nakayama, Hideki Tsutsui, Shintaro Nakano, Daisuke Kobayashi
  • Publication number: 20170141230
    Abstract: According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.
    Type: Application
    Filed: September 16, 2016
    Publication date: May 18, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Keiji IKEDA, Shintaro Nakano, Yuya Maeda, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tsutomu Tezuka
  • Publication number: 20170141131
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a semiconductor layer, a source electrode, a drain electrode, first insulating portion and second insulating portions. The semiconductor layer includes an oxide and is separated from the substrate in a first direction. The source electrode is electrically connected to the semiconductor layer. The drain electrode is electrically connected to the semiconductor layer and is arranged with the source electrode in a second direction crossing the first direction. The first insulating portion is provided between the substrate and the semiconductor layer. The semiconductor layer is provided between the first and second insulating portions. The first insulating portion includes a first silicon nitride layer, and a first aluminum oxide layer stacked with the first silicon nitride layer. The second insulating portion includes a second aluminum oxide layer, and a second silicon nitride layer stacked with the second aluminum oxide layer.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Kentaro MIURA, Yuya MAEDA
  • Patent number: 9640718
    Abstract: According to one embodiment, a method for manufacturing a display element is disclosed. The method can include forming a peeling layer, forming a resin layer, forming a barrier layer, forming an interconnect layer, forming a display layer, and removing. The peeling layer is formed on a major surface of a base body. The major surface has first, second, and third regions. The peeling layer includes first, second, and third peeling portions. The resin layer is formed on the peeling layer. The resin layer includes first and second resin portions. The barrier layer is formed on the first, second, and third peeling portions. The interconnect layer is formed on the barrier layer. The display layer is formed on the interconnect layer. The first peeling portion is removed from the first resin portion and the second peeling portion is removed from the second resin portion.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: May 2, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Miura, Tatsunori Sakano, Tomomasa Ueda, Nobuyoshi Saito, Shintaro Nakano, Yuya Maeda, Hajime Yamaguchi
  • Patent number: 9614099
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer including a first semiconductor portion and a second semiconductor portion being continuous with the first semiconductor portion, a first gate electrode, a second gate electrode, an insulating film. The first semiconductor portion includes a first portion, a second portion and a third portion provided between the first portion and the second portion. The second semiconductor portion includes a fourth portion separated from the first portion, a fifth portion separated from the second portion, and a sixth portion provided between the forth portion and the fifth portion. The first gate electrode is separated from the third portion. The second gate electrode is separated from the sixth portion. The insulating film is provided at a first position between the first gate electrode and the semiconductor layer and at a second position between the second gate electrode and the semiconductor layer.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Yuya Maeda, Masaki Atsuta, Hajime Yamaguchi
  • Publication number: 20170077277
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a source electrode provided on the first nitride semiconductor layer; a drain electrode provided on the first nitride semiconductor layer; a gate electrode provided between the source electrode and the drain electrode; a first film provided between the source electrode and the gate electrode and between the gate electrode and the drain electrode; and a second film provided on the first film. The first film is provided on the first nitride semiconductor layer. The first film has a lower hydrogen diffusion coefficient than a hydrogen diffusion coefficient of a silicon oxide film.
    Type: Application
    Filed: August 12, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Saito, Masahiko Kuraguchi, Tatsuo Shimizu, Shintaro Nakano
  • Publication number: 20170033239
    Abstract: A semiconductor device includes a substrate having a major surface and a thin film transistor on the substrate. The thin film transistor includes an oxynitride semiconductor layer, first and second conductive layers, a first gate electrode and a first insulating layer. The oxynitride semiconductor layer includes a first portion electrically connected to the first conductive layer, a second portion electrically connected to the second conductive layer, and a third portion provided between the first and second portions. The oxynitride semiconductor layer includes indium, gallium, zinc, and nitrogen, a nitrogen content of the oxynitride semiconductor layer being 2 atomic % or less, and a gallium content of the oxynitride semiconductor layer is more than the nitrogen content. The first gate electrode is separated from the third portion in a direction intersecting the first direction; and the first insulating layer is provided between the third portion and the first gate electrode.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Nobuyoshi SAITO, Kentaro MIURA, Yuya MAEDA
  • Publication number: 20160378249
    Abstract: According to an embodiment, an input device includes the following elements. The flexible touch panel includes a sensor area. The touch position detector detects a touch position on the sensor area to generate a detection signal. The deformation position detector detects a deformation position where a deformation amount is not less than a threshold on the sensor area. The input rejection area determination unit determines, based on the deformation position, an input rejection area. The input signal generator fails to output the detection signal as an input signal if the touch position is detected in the input rejection area, and outputs the detection signal as an input signal if the touch position is detected in an area other than the input rejection area.
    Type: Application
    Filed: September 9, 2016
    Publication date: December 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro MIURA, Hajime YAMAGUCHI, Tatsunori SAKANO, Tomomasa UEDA, Nobuyoshi SAITO, Shintaro NAKANO
  • Publication number: 20160380115
    Abstract: A thin film transistor includes semiconductor layer, source electrode, and drain electrode. The semiconductor layer includes first to fifth regions. The third region is provided between the first and second regions. The first region is disposed between the fourth and third regions. The second region is disposed between the fifth and third regions. The semiconductor layer includes an oxide. The source electrode is connected to the first region. The drain electrode is connected to the second region. First thickness of the first region along a second direction is thinner than third thickness along the second direction of each of the third to fifth regions. The second direction crosses a first direction and connects the first region and the source electrode. The first direction connects the first and second regions. Second thickness of the second region along the second direction is thinner than the third thickness.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Yuya MAEDA, Tatsuya OHGURO, Hisayo MOMOSE, Tetsu MOROOKA, Kazuya FUKASE, Nobuki KANREI
  • Publication number: 20160372604
    Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor transistor. The oxide semiconductor transistor includes a semiconductor layer including an oxide semiconductor, the semiconductor layer including a source region and a source electrode. The source electrode includes a source conductive layer including copper, a first tantalum-containing region provided between the source conductive layer and the source region, the first tantalum-containing region including tantalum, a first low nitrogen composition region provided between the first tantalum-containing region and the source region, the first low nitrogen composition region including Ta1?x1Nx1 (0<x1<0.5), and a first high nitrogen composition region provided between the first low nitrogen composition region and the source region, the first high nitrogen composition region including Ta1?x2Nx2 (0.5?x2<1).
    Type: Application
    Filed: August 30, 2016
    Publication date: December 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuya MAEDA, Shintaro NAKANO, Nobuyoshi SAITO, Hajime YAMAGUCHI
  • Patent number: 9494202
    Abstract: An annular groove is provided in a driving-side rotor of a clutch. Guide grooves are provided on a driven-side rotor of the clutch. By moving the driving-side rotor relative to the driven-side rotor, balls are moved that are accommodated in the spaces provided by the sections where the guide grooves and the annular groove face each other. Moving the balls toward the sections where the gap between the driving-side rotor and the driven-side rotor is narrow causes the balls to engage with the driving-side rotor and the driven-side rotor to achieve an engaged state. A disengaged state, in which engagement is cancelled, is achieved by moving the balls to the sections where the gap is wide.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: November 15, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirotaka Sunada, Shintaro Nakano, Daisuke Kobayashi, Akifumi Oosugi
  • Publication number: 20160240561
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer. The third semiconductor is provided between the first semiconductor layer and the second semiconductor layer. A first transistor includes a first gate electrode and a first amorphous semiconductor layer. The first gate electrode and the first amorphous semiconductor layer overlap in a first direction. The first direction is from the first semiconductor layer toward the second semiconductor layer. The first gate electrode is provided between the second semiconductor layer and the first amorphous semiconductor layer.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 18, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi SAITO, Tomio ONO, Shigeya KIMURA, Jumpei TAJIMA, Kentaro MIURA, Shintaro NAKANO, Yuya MAEDA
  • Patent number: 9412765
    Abstract: According to one embodiment, a thin film transistor includes: a substrate; a semiconductor layer; first and second insulating films; and gate, source and drain electrodes. The semiconductor layer is provided on the substrate. The semiconductor layer is made of an oxide having indium. The semiconductor layer has first and second regions and other region. The first insulating film covers a top face of the other region. The second insulating film covers at least a pair of side surfaces of the semiconductor layer. The second insulating film is formed under a condition different from that for the first insulating film. The gate electrode is provided on the first and second insulating films or below the semiconductor layer. The source and drain electrodes are provided on the first and second regions, respectively. The drain and source electrodes sandwich the pair of the side surfaces of the semiconductor layer.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomomasa Ueda, Shintaro Nakano, Nobuyoshi Saito, Kentaro Miura, Yujiro Hara, Hajime Yamaguchi
  • Publication number: 20160169301
    Abstract: An annular groove is provided in a driving-side rotor of a clutch. Guide grooves are provided on a driven-side rotor of the clutch. By moving the driving-side rotor relative to the driven-side rotor, balls are moved that are accommodated in the spaces provided by the sections where the guide grooves and the annular groove face each other. Moving the balls toward the sections where the gap between the driving-side rotor and the driven-side rotor is narrow causes the balls to engage with the driving-side rotor and the driven-side rotor to achieve an engaged state. A disengaged state, in which engagement is cancelled, is achieved by moving the balls to the sections where the gap is wide.
    Type: Application
    Filed: July 18, 2014
    Publication date: June 16, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirotaka SUNADA, Shintaro NAKANO, Daisuke KOBAYASHI, Akifumi OOSUGI
  • Patent number: 9344661
    Abstract: According to an embodiment, a photodetector includes a plurality of photoelectric transducers, a plurality of resistors, and a plurality of resetting sections. Each of the photoelectric transducers is configured to output a detection signal resulting from conversion of received light into an electric charge. Each of the resistors is connected in series with an output end of a corresponding photoelectric transducer at one end of the resistor. Each of the resetting sections is connected in parallel with a corresponding resistor and configured to bring the output end of the corresponding photoelectric transducer to a reset level in response to the detection signal.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: May 17, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuyoshi Saito, Hideyuki Funaki, Shunsuke Kimura, Shintaro Nakano, Go Kawata, Rei Hasegawa
  • Patent number: 9324879
    Abstract: According to one embodiment, a thin film transistor includes a substrate, a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, a source electrode, and a drain electrode. The gate electrode is provided on a part of the substrate. The first insulating film covers the gate electrode. The oxide semiconductor film is provided on the gate electrode via the first insulating film. The second insulating film is provided on a part of the oxide semiconductor film. The source and drain electrodes are respectively connected to first and second portions of the oxide semiconductor film not covered with the second insulating film. The oxide semiconductor film includes an oxide semiconductor. Concentrations of hydrogen contained in the first and second insulating films are not less than 5×1020 atm/cm3, and not more than 1019 atm/cm3, respectively.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: April 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Hajime Yamaguchi
  • Publication number: 20160093742
    Abstract: A semiconductor device according to an embodiment, includes a gate electrode, a first dielectric film, a first oxide semiconductor film, a second dielectric film, a source electrode, a source wire, a drain electrode, and a drain wire. The source wire is arranged on the second dielectric film, and connected to the source electrode. The drain wire is arranged on the second dielectric film, and connected to the drain electrode. At least one of the source wire and the drain wire includes a fringe portion sticking out above a channel region. A barrier film that suppresses intrusion of hydrogen is arranged being in contact with at least one of an upper surface and a lower surface of the fringe portion. A region where the barrier film is not formed is included above the channel region.
    Type: Application
    Filed: March 19, 2015
    Publication date: March 31, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisayo MOMOSE, Tatsuya OHGURO, Tetsu MOROOKA, Kazuya FUKASE, Shintaro NAKANO, Yuya MAEDA, Shuichi TORIYAMA, Nobuki KANREI
  • Patent number: 9293600
    Abstract: A semiconductor element includes a semiconductor layer, a first and a second conductive unit, a gate electrode, and a gate insulating film. The semiconductor layer includes a first portion, a second portion, and a third portion provided between the first portion and the second portion. The first conductive unit is electrically connected to the first portion. The second conductive unit is electrically connected to the second portion. The gate electrode is separated from the first conductive unit, the second conductive unit, and the third portion. The gate electrode opposes the third portion. The gate insulating film is provided between the third portion and the gate electrode. A concentration of nitrogen of the first portion is higher than a concentration of nitrogen of the third portion. A concentration of nitrogen of the second portion is higher than the concentration of nitrogen of the third portion.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: March 22, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Yuya Maeda, Masaki Atsuta, Hajime Yamaguchi
  • Patent number: 9224871
    Abstract: According to one embodiment, a thin film transistor includes a first insulating film, a gate electrode, a semiconductor layer, a gate insulator film, a second insulating film, a source electrode, a tunneling insulating portion, and a drain electrode. The semiconductor layer is provided between the gate electrode and the first insulating film, and includes an amorphous oxide. The gate insulator film is provided between the semiconductor layer and the gate electrode. The second insulating film is provided between the semiconductor layer and the first insulating film. The tunneling insulating portion is provided between the semiconductor layer and the source electrode, and between the semiconductor layer and the drain electrode, and between the first insulating film and the second insulating film. The tunneling insulating portion includes oxygen and at least one selected from aluminum and magnesium. A thickness of the tunneling insulating portion is 2 nanometers or less.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuya Maeda, Hajime Yamaguchi, Tomomasa Ueda, Kentaro Miura, Shintaro Nakano, Nobuyoshi Saito, Tatsunori Sakano