Patents by Inventor Shinya Arai

Shinya Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140021555
    Abstract: A manufacturing method of a semiconductor device according to an embodiment includes forming element isolation regions and active areas on a surface of a semiconductor substrate. A plurality of gate electrodes are formed above the active areas. Recesses that recess below surfaces of the element isolation regions are formed in the active areas by selectively etching the active areas between the gate electrodes. An interlayer dielectric film is deposited on the active areas, the element isolation regions, and the gate electrodes. A contact holes are formed on the recesses by etching the interlayer dielectric film using anisotropic etching. A bottom of each contact holes is widened by further etching the interlayer dielectric film on an inner wall of each contact hole using isotropic etching. Contacts contacting the recesses in the active areas are formed by embedding a conductive material in the contact holes.
    Type: Application
    Filed: February 28, 2013
    Publication date: January 23, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shota ISHIBASHI, Shinya ARAI, Gaku SUDO
  • Publication number: 20140014089
    Abstract: The temperature control system is provided with a lower heat removing unit which is disposed at the bottom of a reactor inside which an exothermic reaction takes place and through which a liquid coolant is flowed, and an upper heat removing unit which is disposed in the reactor further above from the lower heat removing unit and through which the liquid coolant is flowed, recovering reaction heat inside the reactor and controlling a temperature inside the reactor. The lower heat removing unit is supplied with the liquid coolant which is adjusted for temperature by a first temperature adjustment unit, and the upper heat removing unit is supplied with the liquid coolant which is adjusted for temperature by a second temperature adjustment unit different from the first temperature adjustment unit.
    Type: Application
    Filed: March 15, 2012
    Publication date: January 16, 2014
    Applicants: JAPAN OIL, GAS AND METALS NATIONAL CORPORATION, INPEX CORPORATION, NIPPON STEEL & SUMIKIN ENGINEERING CO., LTD., JAPAN PETROLEUM EXPLORATION CO., LTD., COSMO OIL CO., LTD., JX NIPPON OIL & ENERGY CORPORATION
    Inventor: Shinya Arai
  • Publication number: 20140011896
    Abstract: The method for stopping operation of a reactor is provided with a stop step of stopping supply of a synthesis gas containing a carbon monoxide gas and a hydrogen gas into the reactor; a slurry discharge step of discharging slurry from the reactor; a steam supply step of supplying steam higher in temperature than the decomposition temperatures of metal carbonyls into the reactor, thereby discharging gaseous matters inside the reactor; and a carbon monoxide gas detecting step of detecting an amount of carbon monoxide gas contained in the gaseous matters discharged from the reactor. In the steam supply step, supply of the steam is stopped when an amount of the detected carbon monoxide gas continuously declines to be lower than a predetermined reference value.
    Type: Application
    Filed: March 15, 2012
    Publication date: January 9, 2014
    Applicants: Japan Oil, Gas and Metals National Corporation, INPEX CORPORATION, NIPPON STEEL & SUMIKIN ENGINEERING CO., LTD., JAPAN PETROLEUM EXPLORATION CO., LTD., COSMO OIL CO., LTD., JX NIPPON OIL & ENERGY CORPORATION
    Inventor: Shinya Arai
  • Publication number: 20140001556
    Abstract: A memory cell and a peripheral circuit each having a gate electrode are formed on a semiconductor substrate. The periphery of the gate electrodes is covered with an organic insulating layer. A stopper film and a hard mask layer are formed on the gate electrodes and the organic insulating layer, and contact holes are formed between the gate electrodes in a self-aligning manner. Contact electrodes are embedded in the contact holes to provide electrical connection to diffusion layers formed on the semiconductor substrate on either side of each gate electrode.
    Type: Application
    Filed: February 22, 2013
    Publication date: January 2, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Shinya ARAI
  • Publication number: 20130285000
    Abstract: According to one embodiment, the semiconductor device includes a substrate, and an interlayer insulating film that is provided with a plug hole, formed on the substrate. Additionally, the device includes a plug layer formed within the plug hole, a heater layer formed on the plug layer within the plug hole, and a phase change film formed on the heater layer within the plug hole. The device additionally includes a wiring layer formed on the phase change film and the interlayer insulating film.
    Type: Application
    Filed: March 5, 2013
    Publication date: October 31, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Shinya ARAI
  • Publication number: 20130228892
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, isolation regions disposed in the semiconductor substrate, and device regions disposed between the isolation regions in the semiconductor substrate. The device further includes a first line disposed on the device regions and the isolation regions, a line width of the first line on the isolation regions being larger than a line width of the first line on the device regions.
    Type: Application
    Filed: August 21, 2012
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Shinya ARAI
  • Patent number: 8378488
    Abstract: A semiconductor device has an interlayer insulating film that is formed on a semiconductor substrate and has a trench formed therein; a first diffusion barrier film formed on an inner surface of the trench; a Cu wiring layer buried in the trench with the first diffusion barrier film interposed between the Cu wiring layer and the inner surface of the trench; a second diffusion barrier film formed on top of the interlayer insulating film and the Cu wiring layer; an alloy layer primarily containing Cu formed at a first interface between the Cu wiring layer and the second diffusion barrier film; a first reaction layer that is formed at a second interface between the interlayer insulating film and the second diffusion barrier film; and a second reaction layer that is formed on the alloy layer and the first reaction layer.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Arai
  • Publication number: 20120148652
    Abstract: A method of allowing a chemical agent to absorb into a plant body, comprising a step of obtaining a dispersion which disperses aggregates in an aqueous solvent, in which the aggregate has a particle size of 100 nm or less and comprises a chemical agent contained within an amphiphilic substance; and a step of bringing the dispersion obtained in step (1) into contact with at least part of a plant body to thereby allow the aggregates to absorb into the plant body.
    Type: Application
    Filed: August 20, 2010
    Publication date: June 14, 2012
    Applicant: EARTH CHEMICAL CO., LTD.
    Inventors: Masanaga Yamaguchi, Shinya Arai, Atsushi Sato
  • Publication number: 20120126414
    Abstract: A method of manufacturing a semiconductor device, includes forming an insulating film of a material having a low relative dielectric constant on a substrate, forming an SiOCH film on the insulating film in a chamber, forming an SiO2 film continuously on the SiOCH film by reducing a carbon concentration therein in the chamber in which plasma is being generated, performing a plasma etching on the insulating film by using the SiOCH film and the SiO2 film as a hardmask layer, to form a trench in the insulating film, and performing wet etching on a surface of the trench formed in the insulating film, to remove a layer damaged by the plasma etching and process residues.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Inventor: Shinya Arai
  • Patent number: 8129254
    Abstract: A method of manufacturing a semiconductor device, includes forming an insulating film of a material having a low relative dielectric constant on a substrate, forming an SiOCH film on the insulating film in a chamber, forming an SiO2 film continuously on the SiOCH film by reducing a carbon concentration therein in the chamber in which plasma is being generated, performing a plasma etching on the insulating film by using the SiOCH film and the SiO2 film as a hardmask layer, to form a trench in the insulating film, and performing wet etching on a surface of the trench formed in the insulating film, to remove a layer damaged by the plasma etching and process residues.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: March 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Arai
  • Patent number: 8018023
    Abstract: When forming a trench in a porous low-K dielectric (such as an ILD) of a semiconductor device, a carbon-rich layer is formed in the sidewalls of the trench during trench etching. This carbon-rich layer may protect the trench from being excessively etched, which would otherwise form an undesirable hardmask undercut. The carbon-rich layer may be formed simultaneously with and during the etching process, by increasing the amount of carbon available to be absorbed by the ILD during the trench etching process. The existence of the extra available carbon may slow the etching of the carbon-enriched regions of the dielectric.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: September 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinya Arai
  • Patent number: 7799673
    Abstract: A semiconductor device manufacturing method includes: forming a via pattern in an insulating film by use of an alignment mark of a lower wiring line; forming, by use of an alignment mark of the via pattern, an upper wiring groove pattern in an upper insulating film in which the via pattern is embedded; and repeating etching in a self-aligning manner to form a via and a wiring groove in an insulating film previously stacked under the insulating film in which the via pattern has been formed.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: September 21, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Arai, Akihiro Kojima
  • Publication number: 20100181682
    Abstract: A method of manufacturing a semiconductor device, includes forming an insulating film of a material having a low relative dielectric constant on a substrate, forming an SiOCH film on the insulating film in a chamber, forming an SiO2 film continuously on the SiOCH film by reducing a carbon concentration therein in the chamber in which plasma is being generated, performing a plasma etching on the insulating film by using the SiOCH film and the SiO2 film as a hardmask layer, to form a trench in the insulating film, and performing wet etching on a surface of the trench formed in the insulating film, to remove a layer damaged by the plasma etching and process residues.
    Type: Application
    Filed: September 21, 2009
    Publication date: July 22, 2010
    Inventor: Shinya ARAI
  • Publication number: 20100038787
    Abstract: A semiconductor device has an interlayer insulating film that is formed on a semiconductor substrate and has a trench formed therein; a first diffusion barrier film formed on an inner surface of the trench; a Cu wiring layer buried in the trench with the first diffusion barrier film interposed between the Cu wiring layer and the inner surface of the trench; a second diffusion barrier film formed on top of the interlayer insulating film and the Cu wiring layer; an alloy layer primarily containing Cu formed at a first interface between the Cu wiring layer and the second diffusion barrier film; a first reaction layer that is formed at a second interface between the interlayer insulating film and the second diffusion barrier film; and a second reaction layer that is formed on the alloy layer and the first reaction layer.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 18, 2010
    Inventor: Shinya ARAI
  • Publication number: 20090179300
    Abstract: When forming a trench in a porous low-K dielectric (such as an ILD) of a semiconductor device, a carbon-rich layer is formed in the sidewalls of the trench during trench etching. This carbon-rich layer may protect the trench from being excessively etched, which would otherwise form an undesirable hardmask undercut. The carbon-rich layer may be formed simultaneously with and during the etching process, by increasing the amount of carbon available to be absorbed by the ILD during the trench etching process. The existence of the extra available carbon may slow the etching of the carbon-enriched regions of the dielectric.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 16, 2009
    Applicant: Toshiba America Electronic Components, Inc.
    Inventor: Shinya Arai
  • Publication number: 20080286961
    Abstract: A semiconductor device manufacturing method includes: forming a via pattern in an insulating film by use of an alignment mark of a lower wiring line; forming, by use of an alignment mark of the via pattern, an upper wiring groove pattern in an upper insulating film in which the via pattern is embedded; and repeating etching in a self-aligning manner to form a via and a wiring groove in an insulating film previously stacked under the insulating film in which the via pattern has been formed.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 20, 2008
    Inventors: Shinya Arai, Akihiro Kojima
  • Publication number: 20020013737
    Abstract: A shopping information providing server includes a customer database which stores the ID of a user and family information of the user in correspondence with each other, a menu database which stores a menu item, types of material necessary for the menu, and necessary quantities in correspondence with each other, and a special sale information database which stores a providing source, an article for special sale, and its price in correspondence with each other. In accordance with a request from the user, the server provides information of an article to be purchased, including special sale information, checks the reserve articles of the user on the stock information database, and generates and provides a shopping list including the reserve article without stock.
    Type: Application
    Filed: May 29, 2001
    Publication date: January 31, 2002
    Inventor: Shinya Arai