Patents by Inventor Shinya Arai

Shinya Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200235125
    Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
    Type: Application
    Filed: April 9, 2020
    Publication date: July 23, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Shinya ARAI
  • Patent number: 10665598
    Abstract: A semiconductor memory device includes a substrate, a plurality of first electrode layers, a semiconductor layer, a plurality of second electrode layers, and a conductor. The plurality of first electrode layers are arranged to be separated from each other in a first direction above the substrate. The semiconductor layer extends through the plurality of first electrode layers in the first direction. The plurality of second electrode layers are arranged to be separated from each other in the first direction, arranged to be separated from the plurality of first electrode layers in a second direction crossing the first direction, and arranged at substantially the same levels as levels of the plurality of first electrode layers in the first direction. The conductor electrically connects the plurality of second electrode layers to each other. The plurality of second electrode layers are connected in parallel by the conductor.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 26, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Shinya Arai
  • Patent number: 10651199
    Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: May 12, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinya Arai
  • Publication number: 20200144278
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
  • Publication number: 20200122996
    Abstract: A coffee machine 1 having a body part 3, a door 2 that is openably and closably supported by the body part 3 and a cup station at which a cup is placed, the coffee machine 1 supplying milk from a milk nozzle 25 a distal end of which is disposed above the cup, to the cup placed at the cup station, in which the coffee machine 1 includes a movable nozzle support unit 27 that supports the milk nozzle 25 and is disposed in the body part 3 so as to be movable between a first position at which the distal end of the milk nozzle 25 is above the cup while the door 2 is closed and a second position at which the distal end of the milk nozzle 25 is retracted from above the cup and a nozzle movement unit 50 that moves a pusher 52 so as to extend to and retract from the door 2. The pusher 52 is extended to push the movable nozzle support unit 27 and move the movable nozzle support unit 27 to a supply position.
    Type: Application
    Filed: April 23, 2018
    Publication date: April 23, 2020
    Inventors: Takao MATSUMOTO, Shinya ARAI
  • Publication number: 20200093318
    Abstract: It is an object of the present invention to prevent post-drip from a nozzle by means of a simple structure. A coffee machine 1 that supplies coffee into a cup placed at a cup station from a coffee nozzle 23, a distal end of which is disposed above the cup, is provided with a buffer nozzle 61 above the coffee nozzle 23, in which a beverage is supplied to the cup vertically below from the buffer nozzle 61 via the coffee nozzle 23 and a lateral discharge part 82 that discharges coffee post-drip dripping from the buffer nozzle 61 to the side of the coffee nozzle 23 is provided on the side surface of the coffee nozzle 23.
    Type: Application
    Filed: April 23, 2018
    Publication date: March 26, 2020
    Inventor: Shinya ARAI
  • Publication number: 20200075461
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito YOSHIMIZU, Yoshiro SHIMOJO, Shinya ARAI
  • Patent number: 10566339
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 18, 2020
    Assignee: Toshiba Memory Coporation
    Inventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
  • Publication number: 20200043944
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
  • Publication number: 20200006381
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Shinya ARAI
  • Patent number: 10515873
    Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: December 24, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
  • Patent number: 10497717
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka
  • Publication number: 20190355742
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
    Type: Application
    Filed: March 8, 2019
    Publication date: November 21, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki MARUYAMA, Yoshiaki Fukuzumi, Yuki Sugiura, Shinya Arai, Fumie Kikushima, Keisuke Suda, Takashi Ishida
  • Publication number: 20190333928
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.
    Type: Application
    Filed: March 11, 2019
    Publication date: October 31, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi NAGASHIMA, Keisuke NAKATSUKA, Fumitaka ARAI, Shinya ARAI, Yasuhiro UCHIYAMA
  • Patent number: 10461092
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shinya Arai
  • Publication number: 20190326309
    Abstract: A semiconductor memory device includes a substrate, a plurality of first electrode layers, a semiconductor layer, a plurality of second electrode layers, and a conductor. The plurality of first electrode layers are arranged to be separated from each other in a first direction above the substrate. The semiconductor layer extends through the plurality of first electrode layers in the first direction. The plurality of second electrode layers are arranged to be separated from each other in the first direction, arranged to be separated from the plurality of first electrode layers in a second direction crossing the first direction, and arranged at substantially the same levels as levels of the plurality of first electrode layers in the first direction. The conductor electrically connects the plurality of second electrode layers to each other. The plurality of second electrode layers are connected in parallel by the conductor.
    Type: Application
    Filed: September 12, 2018
    Publication date: October 24, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi NAGASHIMA, Shinya ARAI
  • Publication number: 20190296046
    Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
    Type: Application
    Filed: June 12, 2019
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Shinya ARAI
  • Publication number: 20190259777
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasuhito YOSHIMIZU, Akifumi GAWASE, Kei WATANABE, Shinya ARAI
  • Patent number: 10361218
    Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: July 23, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Shinya Arai
  • Publication number: 20190198524
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Application
    Filed: September 12, 2018
    Publication date: June 27, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun FUJIKI, Shinya ARAI, Kotaro FUJII