Patents by Inventor Shinya Arai
Shinya Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10923490Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: GrantFiled: January 9, 2020Date of Patent: February 16, 2021Assignee: Toshiba Memory CorporationInventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
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Publication number: 20210043546Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Applicant: Toshiba Memory CorporationInventors: Yasuhito YOSHIMIZU, Yoshiro SHIMOJO, Shinya ARAI
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Publication number: 20200403001Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.Type: ApplicationFiled: September 3, 2020Publication date: December 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Shinya ARAI
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Patent number: 10854534Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: GrantFiled: November 8, 2019Date of Patent: December 1, 2020Assignee: Toshiba Memory CorporationInventors: Yasuhito Yoshimizu, Yoshiro Shimojo, Shinya Arai
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Publication number: 20200343264Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Applicant: Toshiba Memory CorporationInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Publication number: 20200335517Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.Type: ApplicationFiled: July 1, 2020Publication date: October 22, 2020Applicant: Toshiba Memory CorporationInventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
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Patent number: 10804288Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.Type: GrantFiled: September 21, 2018Date of Patent: October 13, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Shinya Arai
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Publication number: 20200295037Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.Type: ApplicationFiled: September 9, 2019Publication date: September 17, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Jun Iijima, Masayoshi Tagami, Shinya Arai, Takahiro Tomimatsu
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Publication number: 20200286990Abstract: A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.Type: ApplicationFiled: July 12, 2019Publication date: September 10, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro UCHIYAMA, Shinya ARAI, Koichi SAKATA, Takahiro TOMIMATSU
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Patent number: 10756104Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: GrantFiled: September 12, 2018Date of Patent: August 25, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Patent number: 10741583Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.Type: GrantFiled: October 9, 2019Date of Patent: August 11, 2020Assignee: Toshiba Memory CorporationInventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka
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Publication number: 20200235125Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.Type: ApplicationFiled: April 9, 2020Publication date: July 23, 2020Applicant: Toshiba Memory CorporationInventor: Shinya ARAI
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Patent number: 10665598Abstract: A semiconductor memory device includes a substrate, a plurality of first electrode layers, a semiconductor layer, a plurality of second electrode layers, and a conductor. The plurality of first electrode layers are arranged to be separated from each other in a first direction above the substrate. The semiconductor layer extends through the plurality of first electrode layers in the first direction. The plurality of second electrode layers are arranged to be separated from each other in the first direction, arranged to be separated from the plurality of first electrode layers in a second direction crossing the first direction, and arranged at substantially the same levels as levels of the plurality of first electrode layers in the first direction. The conductor electrically connects the plurality of second electrode layers to each other. The plurality of second electrode layers are connected in parallel by the conductor.Type: GrantFiled: September 12, 2018Date of Patent: May 26, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Nagashima, Shinya Arai
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Patent number: 10651199Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.Type: GrantFiled: June 12, 2019Date of Patent: May 12, 2020Assignee: Toshiba Memory CorporationInventor: Shinya Arai
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Publication number: 20200144278Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: ApplicationFiled: January 9, 2020Publication date: May 7, 2020Applicant: Toshiba Memory CorporationInventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
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Publication number: 20200122996Abstract: A coffee machine 1 having a body part 3, a door 2 that is openably and closably supported by the body part 3 and a cup station at which a cup is placed, the coffee machine 1 supplying milk from a milk nozzle 25 a distal end of which is disposed above the cup, to the cup placed at the cup station, in which the coffee machine 1 includes a movable nozzle support unit 27 that supports the milk nozzle 25 and is disposed in the body part 3 so as to be movable between a first position at which the distal end of the milk nozzle 25 is above the cup while the door 2 is closed and a second position at which the distal end of the milk nozzle 25 is retracted from above the cup and a nozzle movement unit 50 that moves a pusher 52 so as to extend to and retract from the door 2. The pusher 52 is extended to push the movable nozzle support unit 27 and move the movable nozzle support unit 27 to a supply position.Type: ApplicationFiled: April 23, 2018Publication date: April 23, 2020Inventors: Takao MATSUMOTO, Shinya ARAI
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Publication number: 20200093318Abstract: It is an object of the present invention to prevent post-drip from a nozzle by means of a simple structure. A coffee machine 1 that supplies coffee into a cup placed at a cup station from a coffee nozzle 23, a distal end of which is disposed above the cup, is provided with a buffer nozzle 61 above the coffee nozzle 23, in which a beverage is supplied to the cup vertically below from the buffer nozzle 61 via the coffee nozzle 23 and a lateral discharge part 82 that discharges coffee post-drip dripping from the buffer nozzle 61 to the side of the coffee nozzle 23 is provided on the side surface of the coffee nozzle 23.Type: ApplicationFiled: April 23, 2018Publication date: March 26, 2020Inventor: Shinya ARAI
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Publication number: 20200075461Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.Type: ApplicationFiled: November 8, 2019Publication date: March 5, 2020Applicant: Toshiba Memory CorporationInventors: Yasuhito YOSHIMIZU, Yoshiro SHIMOJO, Shinya ARAI
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Patent number: 10566339Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: GrantFiled: August 31, 2017Date of Patent: February 18, 2020Assignee: Toshiba Memory CoporationInventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
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Publication number: 20200043944Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.Type: ApplicationFiled: October 9, 2019Publication date: February 6, 2020Applicant: Toshiba Memory CorporationInventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA