Patents by Inventor Shinya Fujioka

Shinya Fujioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10559342
    Abstract: A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a temperature sensor, a dynamic memory cell array, a control circuit, a plurality of power supply circuits and a power control circuit. The temperature sensor senses an operating temperature of the DRAM. The control circuit is coupled to a dynamic memory cell array, and accesses and manages the dynamic memory cell array. The power supply circuits powers the dynamic memory cell array and the control circuit. The power control circuit controls power outputs of the power supply circuits. When the DRAM enters the self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the DRAM.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 11, 2020
    Assignee: Windbond Electronics Corp.
    Inventors: Shinya Fujioka, Hitoshi Ikeda
  • Publication number: 20190385668
    Abstract: A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a temperature sensor, a dynamic memory cell array, a control circuit, a plurality of power supply circuits and a power control circuit. The temperature sensor senses an operating temperature of the DRAM. The control circuit is coupled to a dynamic memory cell array, and accesses and manages the dynamic memory cell array. The power supply circuits powers the dynamic memory cell array and the control circuit. The power control circuit controls power outputs of the power supply circuits. When the DRAM enters the self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the DRAM.
    Type: Application
    Filed: August 24, 2018
    Publication date: December 19, 2019
    Applicant: Winbond Electronics Corp.
    Inventors: Shinya Fujioka, Hitoshi Ikeda
  • Patent number: 10357747
    Abstract: A method for producing a spiral wound separation membrane element includes preparing a composite semipermeable membrane having a skin layer on the surface of a porous support. The method further includes forming on the skin layer a protective layer containing 35 mg/m2 or more of an anionic polyvinyl alcohol to prepare a protective layer-equipped composite semipermeable membrane, preparing an unwashed spiral wound separation membrane element from the protective layer-equipped composite semipermeable membrane, and passing wash water through the unwashed spiral wound separation membrane element to remove the protective layer on the skin layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 23, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shinya Nishiyama, Taisuke Yamaguchi, Takahisa Konishi, Hiroki Fujioka, Takashi Kamada, Shinichi Inoue
  • Patent number: 10328343
    Abstract: A game apparatus being a non-limiting example information processing apparatus includes a display, and a game screen of a baseball game is displayed on the display. In a defensive (fielding team) side, in the game screen, a batter object and a catcher object are displayed, and an index object is displayed in front of the catcher object. Using the index object, a player designates a target position of a position that a ball object is to be thrown (pitching course) and a pitch type of the ball object, and instructs pitching. Even if the player designates the target position and the pitch type in any order, the target position and the pitch type can be set according to a designated order.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: June 25, 2019
    Assignee: NINTENDO CO., LTD.
    Inventors: Toshiharu Izuno, Shinya Saito, Naohiro Hayashi, Kenji Fujioka, Katsutoshi Sato
  • Patent number: 9881246
    Abstract: In a semiconductor device that generates a power supply voltage from an RF carrier signal received by an antenna through the use of a rectification circuit, rectification circuits, each including a plurality of capacitors and a plurality of diodes, are connected in multistage. The rectification circuits includes limiter circuits that are turned on at a voltage larger than an on-voltage of the diodes, clamp cathodes of the diodes at a first voltage. The limiter circuits and the diodes are connected in parallel between the capacitors connected to the antenna connection terminal and a node supplied reference potential VSS of the power supply voltage.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: January 30, 2018
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Akihiko Sugata, Kohji Nozoe, Tsuzumi Ninomiya, Shinya Fujioka
  • Patent number: 9350746
    Abstract: A transmission network system includes a network terminating device connected to a user terminal and an authentication information device connected to the network terminating device through a transmission network. The transmission network is connected to a reference clock that holds a reference time. The network terminating device includes a terminating internal clock that synchronizes with the reference clock, when receiving a first frame from the user terminal, generates a second frame including a time outputted from the terminating internal clock as a request time on the basis of the first frame, and transmits the second frame to the authentication information device. The authentication information device generates time authentication information based on the request time included in the received second frame, generates a third frame including the generated time authentication information, and transmits the third frame to the transmission network.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 24, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Shinya Fujioka, Yoshihiro Ashi, Masahiko Mizutani
  • Publication number: 20160055406
    Abstract: In a semiconductor device that generates a power supply voltage from an RF carrier signal received by an antenna through the use of a rectification circuit, rectification circuits, each including a plurality of capacitors and a plurality of diodes, are connected in multistage. The rectification circuits includes limiter circuits that are turned on at a voltage larger than an on-voltage of the diodes, clamp cathodes of the diodes at a first voltage. The limiter circuits and the diodes are connected in parallel between the capacitors connected to the antenna connection terminal and a node supplied reference potential VSS of the power supply voltage.
    Type: Application
    Filed: July 28, 2015
    Publication date: February 25, 2016
    Inventors: Akihiko SUGATA, Kohji Nozoe, Tsuzumi Ninomiya, Shinya Fujioka
  • Patent number: 9147441
    Abstract: A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus lines 26 provided respectively associated with the plurality of memory blocks; a plurality of input/output ports 22a, 22b; a selector 28a, 28b selectively connecting each of the plurality of bus lines to one of the plurality of input/output ports; and a setting unit 38a, 38b setting a connection of the selector.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: September 29, 2015
    Assignee: SOCIONEXT INC.
    Inventor: Shinya Fujioka
  • Patent number: 9135983
    Abstract: When a voltage monitoring circuit detects that a supplied voltage is in a state of being less than a certain voltage at a time of performing writing of data with respect to a memory cell of a memory core having a refresh function, a flag is set in a register circuit, an address at which the writing is performed is held, and the memory core is made to execute rewriting by a refresh operation with respect to the held address, in accordance with the flag set in the register circuit, thereby enabling an increase in speed of operation while securing a retention life of memory data, and enabling a reduction in power consumption without lowering a processing capability even if the supplied voltage is lowered.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: September 15, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Shinya Fujioka
  • Publication number: 20150235690
    Abstract: When a voltage monitoring circuit detects that a supplied voltage is in a state of being less than a certain voltage at a time of performing writing of data with respect to a memory cell of a memory core having a refresh function, a flag is set in a register circuit, an address at which the writing is performed is held, and the memory core is made to execute rewriting by a refresh operation with respect to the held address, in accordance with the flag set in the register circuit, thereby enabling an increase in speed of operation while securing a retention life of memory data, and enabling a reduction in power consumption without lowering a processing capability even if the supplied voltage is lowered.
    Type: Application
    Filed: January 13, 2015
    Publication date: August 20, 2015
    Inventor: Shinya FUJIOKA
  • Patent number: 9053757
    Abstract: A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: June 9, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Shinya Fujioka
  • Publication number: 20150103643
    Abstract: A transmission network is comprised of a network management system for collectively managing and controlling a plurality of transmission devices coupled mutually through transmission routes and the transmission network as well. The network management system includes a plane management table adapted to manage transmission planes defined as a set of paths in the transmission network, and the plane management table has the function to set and manage a transmission plane (working plane) applied during normal operation and besides, a single or a plurality of transmission planes (protection planes) applicable in the event of occurrence of a fault in the transmission network. Then, when a fault occurs in the transmission network, the network management system changes the applied plane to a suitable transmission plane.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Applicant: Hitachi, Ltd.
    Inventors: SHINYA FUJIOKA, Yoshihiro ASHI, Masahiko MIZUTANI, Hideki ENDO
  • Publication number: 20140215566
    Abstract: A transmission network system includes a network terminating device connected to a user terminal and an authentication information device connected to the network terminating device through a transmission network. The transmission network is connected to a reference clock that holds a reference time. The network terminating device includes a terminating internal clock that synchronizes with the reference clock, when receiving a first frame from the user terminal, generates a second frame including a time outputted from the terminating internal clock as a request time on the basis of the first frame, and transmits the second frame to the authentication information device. The authentication information device generates time authentication information based on the request time included in the received second frame, generates a third frame including the generated time authentication information, and transmits the third frame to the transmission network.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 31, 2014
    Inventors: Shinya FUJIOKA, Yoshihiro ASHI, Masahiko MIZUTANI
  • Publication number: 20140169071
    Abstract: A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped.
    Type: Application
    Filed: September 11, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Shinya FUJIOKA
  • Publication number: 20140085960
    Abstract: A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus lines 26 provided respectively associated with the plurality of memory blocks; a plurality of input/output ports 22a, 22b; a selector 28a, 28b selectively connecting each of the plurality of bus lines to one of the plurality of input/output ports; and a setting unit 38a, 38b setting a connection of the selector.
    Type: Application
    Filed: August 22, 2013
    Publication date: March 27, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Shinya FUJIOKA
  • Patent number: 8667058
    Abstract: When data is disclosed to a plurality of users by using a transfer network and a transfer apparatus, data disclosure time control which cannot be adversely affected by the users is performed to reduce the difference in data disclosure time among the users. A transfer network system includes a distribution server serving as a data-distribution-source transfer apparatus, and a network terminal connected to distribution-destination user equipment. The distribution server and the network terminal each have a time keeping function and a time synchronization function for matching the time of the time keeping function with a master clock. The distribution server sends in advance disclosure data and disclosure time to the network terminal. When the time of the time keeping function of the network terminal matches the disclosure time, the network terminal sends the disclosure data to the user equipment.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: March 4, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Shinya Fujioka, Yoshihiro Ashi, Masahiko Mizutani
  • Patent number: 8619487
    Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: December 31, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinya Fujioka, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
  • Publication number: 20130332761
    Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.
    Type: Application
    Filed: August 6, 2013
    Publication date: December 12, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinya FUJIOKA, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
  • Publication number: 20130326246
    Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.
    Type: Application
    Filed: August 6, 2013
    Publication date: December 5, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinya FUJIOKA, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato
  • Publication number: 20130326247
    Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.
    Type: Application
    Filed: August 6, 2013
    Publication date: December 5, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Shinya FUJIOKA, Tomohiro Kawakubo, Koichi Nishimura, Kotoku Sato