Abstract: A semiconductor memory device that can easily recognize the content of errors in data is provided. The semiconductor memory device includes a memory cell array, an error detection and correction circuit, and an input / output circuit. The memory cell array includes a plurality of memory cells. The error detection and correction circuit detects and corrects error bits included in the data output by the memory cell array. The error detection and correction circuit activates an error detection signal when the data includes a correctable error bit. The input / output circuit stops the clocking of the data strobe signal output with data when the data includes uncorrectable error bits.

Abstract: A semiconductor memory device capable of suppressing an increase in power consumption and avoiding data destruction due to the row hammer problem is provided. The semiconductor memory device includes a refresh control unit (first control unit) that sets a memory cell refresh interval based on information about a memory cell refresh interval included in a predetermined command input from the outside.

Abstract: A battery charging control device for a vehicle is provided, which includes a motor, a high-voltage battery, a low-voltage battery, a charging connecting device, an auxiliary charging device, a temporary storage device, a storage device, a write processing device which performs write processing for writing and storing in the storage device information stored in the temporary storage device, and a control device which includes a determination module and a charging control module.

Abstract: To provide a contactor failure determination apparatus capable of appropriately determining failure of a contactor provided in a vehicle, a voltage sensor capable of detecting rising or dropping of a voltage of a second circuit including an external charger is provided. When an external charging request is made, a first control for closing each external charging contactor is executed, a second control for closing a pre-charge contactor is executed after execution of the first control, a third control for closing a second main contactor is executed after execution of the second control, and response to the voltage sensor detecting that the voltage of the second circuit has not risen after execution of the third control, it is determined that at least one of the external charging contactors has failed in an open state.

Abstract: The vehicle power supply apparatus includes: a drive power supply that supplies electric power to a motor for generating drive power; an auxiliary power supply that supplies electric power to a motor controller and door lock controllers; and a backup power supply. A control method for the vehicle power supply apparatus includes: discharging the in-vehicle equipment by using the electric power that is supplied from the backup power supply when it is determined that a vehicle has collided with an obstacle; and operating the door lock controllers by using the electric power that is supplied from the backup power supply after a lapse of a specified time period since initiation timing of the discharging step so as to unlock doors.

Abstract: To provide a battery heater failure diagnostic device for a vehicle capable of diagnosing failure of a battery heater with a high degree of accuracy, a battery output sensor capable of detecting a battery output value that is a current value or a voltage value of a battery is provided. When a specified failure diagnosis condition is satisfied, a first control for stopping actuation of a battery heater and at least one non-heater device and a second control for actuating the battery heater while maintaining a stop of the actuation of the at least one non-heater device after execution of the first control are executed. The failure of the battery heater is diagnosed based on battery output values detected by the battery output sensor during execution of the first control and during execution of the second control.

Abstract: To provide a contactor failure determination apparatus capable of appropriately determining failure of a contactor provided in a vehicle, a voltage sensor capable of detecting rising or dropping of a voltage of a second circuit including an external charger is provided. When a vehicle start request is made, a first control for closing one external charging contactor is executed, a second control for closing a pre-charge contactor is executed after execution of the first control, a third control for closing a main contactor, which is not parallel with the pre-charge contactor, is executed after execution of the second control, and in response to the voltage sensor detecting that the voltage of the second circuit has risen after execution of the third control, it is determined that the other external charging contactor has failed in a closed state.

Abstract: A semiconductor memory device capable of suppressing an increase in power consumption and avoiding data destruction due to the row hammer problem is provided. The semiconductor memory device includes a refresh control unit (first control unit) that sets a memory cell refresh interval based on information about a memory cell refresh interval included in a predetermined command input from the outside.

Abstract: A memory device and a method for input/output buffer control are provided. The memory device includes a pseudo static random access memory and a controller. The pseudo static random access memory includes an input/output circuit having a fast mode circuit and a slow mode circuit. The controller adjusts a power supply voltage and a clock frequency according to an operation mode of the memory device, and generates a register setting code based on an adjusted power supply voltage and an adjusted clock frequency. The pseudo static random access memory enables one of the fast mode circuit and the slow mode circuit according to the register setting code, and disables the other of the fast mode circuit and the slow mode circuit.

Abstract: A memory device and a method for input/output buffer control are provided. The memory device includes a pseudo static random access memory and a controller. The pseudo static random access memory includes an input/output circuit having a fast mode circuit and a slow mode circuit. The controller adjusts a power supply voltage and a clock frequency according to an operation mode of the memory device, and generates a register setting code based on an adjusted power supply voltage and an adjusted clock frequency. The pseudo static random access memory enables one of the fast mode circuit and the slow mode circuit according to the register setting code, and disables the other of the fast mode circuit and the slow mode circuit.

Abstract: A memory apparatus includes a pseudo static random access memory and a controller. The controller is configured to provide an external command to the pseudo static random access memory. When the memory apparatus starts a burst read operation or a burst write operation, the controller provides a plurality of page starting addresses to the pseudo static random access memory, and the pseudo static random access memory sequentially performs the burst read operation or the burst write operation according to a sequence of receiving the page starting addresses.

Abstract: The vehicle power supply apparatus includes: a drive power supply that supplies electric power to a motor for generating drive power; an auxiliary power supply that supplies electric power to a motor controller and door lock controllers; and a backup power supply. A control method for the vehicle power supply apparatus includes: discharging the in-vehicle equipment by using the electric power that is supplied from the backup power supply when it is determined that a vehicle has collided with an obstacle; and operating the door lock controllers by using the electric power that is supplied from the backup power supply after a lapse of a specified time period since initiation timing of the discharging step so as to unlock doors.

Abstract: A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a temperature sensor, a dynamic memory cell array, a control circuit, a plurality of power supply circuits and a power control circuit. The temperature sensor senses an operating temperature of the DRAM. The control circuit is coupled to a dynamic memory cell array, and accesses and manages the dynamic memory cell array. The power supply circuits powers the dynamic memory cell array and the control circuit. The power control circuit controls power outputs of the power supply circuits. When the DRAM enters the self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the DRAM.

Abstract: A dynamic random access memory (DRAM) and an operation method thereof are provided. The DRAM includes a temperature sensor, a dynamic memory cell array, a control circuit, a plurality of power supply circuits and a power control circuit. The temperature sensor senses an operating temperature of the DRAM. The control circuit is coupled to a dynamic memory cell array, and accesses and manages the dynamic memory cell array. The power supply circuits powers the dynamic memory cell array and the control circuit. The power control circuit controls power outputs of the power supply circuits. When the DRAM enters the self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the DRAM.

Abstract: In a semiconductor device that generates a power supply voltage from an RF carrier signal received by an antenna through the use of a rectification circuit, rectification circuits, each including a plurality of capacitors and a plurality of diodes, are connected in multistage. The rectification circuits includes limiter circuits that are turned on at a voltage larger than an on-voltage of the diodes, clamp cathodes of the diodes at a first voltage. The limiter circuits and the diodes are connected in parallel between the capacitors connected to the antenna connection terminal and a node supplied reference potential VSS of the power supply voltage.

Abstract: A transmission network system includes a network terminating device connected to a user terminal and an authentication information device connected to the network terminating device through a transmission network. The transmission network is connected to a reference clock that holds a reference time. The network terminating device includes a terminating internal clock that synchronizes with the reference clock, when receiving a first frame from the user terminal, generates a second frame including a time outputted from the terminating internal clock as a request time on the basis of the first frame, and transmits the second frame to the authentication information device. The authentication information device generates time authentication information based on the request time included in the received second frame, generates a third frame including the generated time authentication information, and transmits the third frame to the transmission network.

Abstract: In a semiconductor device that generates a power supply voltage from an RF carrier signal received by an antenna through the use of a rectification circuit, rectification circuits, each including a plurality of capacitors and a plurality of diodes, are connected in multistage. The rectification circuits includes limiter circuits that are turned on at a voltage larger than an on-voltage of the diodes, clamp cathodes of the diodes at a first voltage. The limiter circuits and the diodes are connected in parallel between the capacitors connected to the antenna connection terminal and a node supplied reference potential VSS of the power supply voltage.

Abstract: A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus lines 26 provided respectively associated with the plurality of memory blocks; a plurality of input/output ports 22a, 22b; a selector 28a, 28b selectively connecting each of the plurality of bus lines to one of the plurality of input/output ports; and a setting unit 38a, 38b setting a connection of the selector.

Abstract: When a voltage monitoring circuit detects that a supplied voltage is in a state of being less than a certain voltage at a time of performing writing of data with respect to a memory cell of a memory core having a refresh function, a flag is set in a register circuit, an address at which the writing is performed is held, and the memory core is made to execute rewriting by a refresh operation with respect to the held address, in accordance with the flag set in the register circuit, thereby enabling an increase in speed of operation while securing a retention life of memory data, and enabling a reduction in power consumption without lowering a processing capability even if the supplied voltage is lowered.

Abstract: When a voltage monitoring circuit detects that a supplied voltage is in a state of being less than a certain voltage at a time of performing writing of data with respect to a memory cell of a memory core having a refresh function, a flag is set in a register circuit, an address at which the writing is performed is held, and the memory core is made to execute rewriting by a refresh operation with respect to the held address, in accordance with the flag set in the register circuit, thereby enabling an increase in speed of operation while securing a retention life of memory data, and enabling a reduction in power consumption without lowering a processing capability even if the supplied voltage is lowered.