Abstract: A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped.

Abstract: A transmission network is comprised of a network management system for collectively managing and controlling a plurality of transmission devices coupled mutually through transmission routes and the transmission network as well. The network management system includes a plane management table adapted to manage transmission planes defined as a set of paths in the transmission network, and the plane management table has the function to set and manage a transmission plane (working plane) applied during normal operation and besides, a single or a plurality of transmission planes (protection planes) applicable in the event of occurrence of a fault in the transmission network. Then, when a fault occurs in the transmission network, the network management system changes the applied plane to a suitable transmission plane.

Abstract: A transmission network system includes a network terminating device connected to a user terminal and an authentication information device connected to the network terminating device through a transmission network. The transmission network is connected to a reference clock that holds a reference time. The network terminating device includes a terminating internal clock that synchronizes with the reference clock, when receiving a first frame from the user terminal, generates a second frame including a time outputted from the terminating internal clock as a request time on the basis of the first frame, and transmits the second frame to the authentication information device. The authentication information device generates time authentication information based on the request time included in the received second frame, generates a third frame including the generated time authentication information, and transmits the third frame to the transmission network.

Abstract: A semiconductor memory device including a plurality of memory blocks each including a first command generating circuit which generates a first command; a control circuit which controls the memory core based on the first command or based on a second command inputted via the input/output port; and an arbitration circuit which outputs a first delay signal to the control circuit of one memory block of the plurality of memory blocks, the first delay signal which delays a start of an execution of the first command, in a first case when the first command generated by the first command generating circuit of the one memory block and the second command inputted via the input/output port of another memory block of the plurality of memory blocks are overlapped.

Abstract: A semiconductor memory device including a plurality of memory blocks MBA0, MBA1, MBB0, MBB1; a plurality of bus lines 26 provided respectively associated with the plurality of memory blocks; a plurality of input/output ports 22a, 22b; a selector 28a, 28b selectively connecting each of the plurality of bus lines to one of the plurality of input/output ports; and a setting unit 38a, 38b setting a connection of the selector.

Abstract: When data is disclosed to a plurality of users by using a transfer network and a transfer apparatus, data disclosure time control which cannot be adversely affected by the users is performed to reduce the difference in data disclosure time among the users. A transfer network system includes a distribution server serving as a data-distribution-source transfer apparatus, and a network terminal connected to distribution-destination user equipment. The distribution server and the network terminal each have a time keeping function and a time synchronization function for matching the time of the time keeping function with a master clock. The distribution server sends in advance disclosure data and disclosure time to the network terminal. When the time of the time keeping function of the network terminal matches the disclosure time, the network terminal sends the disclosure data to the user equipment.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Abstract: A transmission network is comprised of a network management system for collectively managing and controlling a plurality of transmission devices coupled mutually through transmission routes and the transmission network as well. The network management system includes a plane management table adapted to manage transmission planes defined as a set of paths in the transmission network, and the plane management table has the function to set and manage a transmission plane (working plane) applied during normal operation and besides, a single or a plurality of transmission planes (protection planes) applicable in the event of occurrence of a fault in the transmission network. Then, when a fault occurs in the transmission network, the network management system changes the applied plane to a suitable transmission plane.

Abstract: A packet transport system to which the present invention is applied includes an edge node accommodating an access network at an edge, and a core node of carrying out a processing of assorting a frame gathered from a plurality of the edge nodes, the edge node provides a label to the frame flowing in from the access network, and the packet transport system transmits the frame in reference to the label. The edge node includes a priority information providing portion of changing a piece of priority information provided to the frame flowing in from the access network in accordance with a congested state of the core node, and a priority previously set to a path specified by the label.

Abstract: When a neighbor ONU receives a signal with light intensity high enough to secure communication between an OLT and a remote ONU, the light intensity may be excessively high to damage a receiver of the neighbor ONU. In order to avoid such a problem, each ONU is notified of a downstream signal transmission plan (downstream light intensity map) prior to transmission of a downstream signal. Each ONU receives the downstream light intensity map (light intensity transmission schedule of downstream signal) in advance. Thus, the neighbor ONU can block or attenuate an optical signal addressed to the remote ONU, and the remote ONU can determine normal operation even when the remote ONU cannot receive a signal addressed to the neighbor ONU. Thus, the remote ONU can be prevented from issuing a wrong error signal.

Abstract: When data is disclosed to a plurality of users by using a transfer network and a transfer apparatus, data disclosure time control which cannot be adversely affected by the users is performed to reduce the difference in data disclosure time among the users. A transfer network system includes a distribution server serving as a data-distribution-source transfer apparatus, and a network terminal connected to distribution-destination user equipment. The distribution server and the network terminal each have a time keeping function and a time synchronization function for matching the time of the time keeping function with a master clock. The distribution server sends in advance disclosure data and disclosure time to the network terminal. When the time of the time keeping function of the network terminal matches the disclosure time, the network terminal sends the disclosure data to the user equipment.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.