Abstract: Switching transistors 20, 22, 22P, 21, 23 and 23P and a portion of control circuit for transistors 20 and 21 constitutes a bit line reset circuit on memory cell side. In reading `H` from the memory cell connected to a bit line BLC or *BLC, the both bit lines are set at a higher reset potential Vii, while in reading `L`, the both bit lines are reset at a lower reset potential Vss. Transfer gates 10 and 11 are turned off before sufficient amplification of a potential difference between the bit lines BL and *BL. The operation of restoring into a memory cell read destructively from is performed in parallel with the operation of bit line reset.

Abstract: A step-up circuit includes a selection control circuit 50 for activating a start/stop signal STP by detecting an external power-supply voltage Vcc, which is stable at 3.3 V, to reach 2.0 V or more, a ring oscillator circuit 30 for generating and outputting a clock of a high frequency Fs when the start/stop signal STP is inactive, a ring oscillator circuit 10 for generating a clock of a low frequency fo, a selection circuit 40 for selecting the output of the oscillator 30 when the start/stop signal STP is inactive and for selecting the output of the oscillator 10 when the start/stop signal is active, and a charging pump circuit 20 driven by the clocks. High frequency Fs is initially used to quickly bring an output voltage up to a desired operating level and low frequency fo is used, in order to conserve power, to maintain the operating level once a predetermined level of the external power supply voltage Vcc has been reached in order to conserve power.

Abstract: A semiconductor integrated circuit having a DRAM, or the like, includes a memory cell block containing a plurality of memory cells, and a core circuit portion for selecting and activating a specified memory cell inside the memory cell block, and is constituted so that a step-up voltage is applied to the core circuit portion at the time of an activated state. The semiconductor integrated circuit further includes a step-up voltage lowering unit for lowering the step-up voltage by a predetermined value and a unit for selectively supplying the step-up voltage and an output voltage of the step-up voltage lowering unit to the core circuit portion.

Abstract: A clock generator including a DLL occupying a small area and a semiconductor device including the clock generator have been disclosed. In the clock generator for generating a plurality of clocks optimally adjusted in phase for a plurality of objects on the basis of a received clock, the DLL is structured hierarchically. A first DLL of a parent level is used in common and second DLLs of child levels are associated with input signals.

Abstract: A semiconductor memory device which employs a hierarchical word-decode scheme for word selection includes sub-word lines provided for each of column blocks, a control circuit selecting one of the column blocks corresponding to a currently accessed column address in a first case where a currently accessed row address is different from a successively accessed row address, and selecting all of the column blocks in a second case where the currently accessed row address is the same as the successively accessed row address, and a sub-word decoder selectively activating the sub-word lines with respect to all of one or more column blocks selected by the control circuit.

Abstract: A semiconductor integrated circuit has a de-skew circuit for reducing a skew of an incoming signal from a specific circuit with respect to a synchronous clock signal. The de-skew circuit controls the phase of an outgoing signal to be transmitted from the semiconductor integrated circuit to the specific circuit in response to the skew of the input signal. This arrangement decreases not only a skew of incoming signals from the specific circuit but also a skew of outgoing signals to the specific circuit.

Abstract: A semiconductor device operable in a selected mode which is selected from a plurality of operation modes, a number of the operation modes being more than two. The semiconductor device includes a plurality of voltage supply circuits for supplying an internal voltage to internal circuits of the semiconductor device, and a control circuit for driving a predetermined number of the voltage supply circuits based on a signal indicating the selected mode, the control circuit changing the predetermined number for each of the operation modes.

Abstract: A volatile memory device or a refreshing method for refreshing information stored in a plurality of memory cells, comprises: a plurality of banks each having a plurality of cell array blocks each of which have a plurality of memory cells and a decoder portion for selecting the memory cells; an address buffer being supplied with an address signal; and a plurality of predecoders associated respectively with the banks, for being supplied with an output signal from the address buffer and supplying predecoded signals to the associated banks. When the volatile memory device is refreshed, the predecoder associated with one of the banks which is selected is activated, and a plurality of cell array blocks in the selected bank are simultaneously selected, and the predecoders associated with the banks which are unselected are inactivated. According to the present invention, the high speed refresh and low power consumption can be realized.

Abstract: A semiconductor memory has a plurality of memory arrays, and a plurality of selection circuits. Each of the memory arrays has a plurality of memory blocks. The selection circuits is provided to the memory arrays and is used to independently disable a defective memory block and select a normal memory block in the memory array. Therefore, the semiconductor memory enables to increase the number of partial good memories (half good memories: half capacity memory), and to increase a product yield.