Abstract: The constant-current generator comprises a bias transistor whose drain and gate are connected to each other, and an outputting transistor. The threshold voltage of the outputting transistor is smaller than that of the bias transistor. The outputting transistor has the same source voltage and the same gate voltage as those of the bias transistor. Therefore, the gate-to-source voltages of the outputting transistor and the bias transistor are always kept equal. On the other hand, the drain-to-source current of the outputting transistor becomes larger than that of the bias transistor in accordance with the difference between the threshold voltages of the outputting transistor and the bias transistor. Accordingly, the outputting transistor can output a stable drain-to-source current even when the drain voltage of the bias transistor has shifted to lower the gate-to-source voltage thereof.

Abstract: The present invention is a memory circuit for writing prescribed numbers of bits of write data, determined according to the burst length, in response to write command, comprising: a first stage for inputting, and then holding, row addresses and column addresses simultaneously with the write command; a second stage having a memory core connected to the first stage via a pipeline switch, wherein the row addresses and column addresses are decoded, and word line and sense amps are activated; a third stage for inputting the write data serially and sending the write data to the memory core in parallel; and a serial data detection circuit for generating write-pipeline control signal for making the pipeline switch conduct, after the prescribed number of bits of write data has been inputted. According to the present invention, in an FCRAM exhibiting a pipeline structure, the memory core in the second stage can be activated after safely fetching the write data in the burst length.

Abstract: A semiconductor memory device having a self-refresh operation includes a first circuit generating a first signal that specifies a first self-refresh cycle by a non-volatile circuit element provided in the semiconductor memory device, a second circuit receiving a second signal that specifies a second self-refresh cycle via a terminal that is used in common to another signal, and a third circuit generating a pulse signal having one of the first and second self-refresh cycles, the pulse signal being related to the self-refresh operation.

Abstract: A semiconductor memory device having a self-refresh operation includes a detection circuit generating a detection signal when detecting a change of a given input signal, and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation.

Abstract: A semiconductor memory device includes bit lines which transfer data of memory cells, a plurality of first sense amplifier circuits connected to odd-number lines of the bit lines, a plurality of second sense amplifier circuits connected to even-number lines of the bit lines, and a clamp-voltage generation circuit which supplies a first clamp voltage to the first sense amplifier circuits, and supplies a second clamp voltage to the second sense amplifier circuits, whereby during test operation, the odd-number lines are clamped to the first clamp voltage, and the even-number lines are clamped to the second clamp voltage.

Abstract: A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.

Abstract: A semiconductor memory device is provided. The semiconductor memory device comprises at least two memory cell arrays, a sense amplifier shared by the memory cell arrays, at least two transfer gates connected respectively between each of the memory cell arrays and the sense amplifier, a first voltage supplier supplying a first voltage to the transfer gates, and a second voltage supplier supplying a second voltage to the transfer gates. The second voltage is higher than the first voltage.

Abstract: A semiconductor memory device having a self-refresh function includes a detection circuit detecting a change of an output enable signal and generating a state transition detection signal, and a decision circuit comparing the state transition detection signal and a refresh request signal internally generated and generating a signal that indicates a corresponding circuit operation.

Abstract: An address signal is transmited to a decoder before the activation of a control signal operating a memory cell. Here, the decoder is inactivated. Subsequently, after the activation of the control signal, the reception of a new address signal is inhibited, and the decoder is activated at the same time. Therefore, the decoder starts operating at an earlier timing of the operating cycle, outputting a decoding signal. This means reduction in access time. Moreover, the reception of a new address signal is inhibited after the activation of the control signal. This prevents the decoder from decoding incorrect address signals ascribable to noises and the like, thereby avoiding malfunctions.

Abstract: A semiconductor device includes a plurality of word lines selectable in a predetermined mode, and a circuit that precharges the plurality of word lines selected in the predetermined mode in a time division manner.

Abstract: A memory circuit including a memory cell array. The memory cell array has a first word line group connected to a pair of memory cells associated with a first bit line pair including first and third bit lines, and a second word line group, connected to a pair of memory cells associated with a second bit line pair including second and fourth bit lines. First and second sense amplifier groups are positioned one on each side of the memory array, and are connected to the first and second bit line pair, respectively. When any word line of the first word line group is driven, the first sense amplifier group is activated to drive the first word line group in reverse phase, and the second sense amplifier group is kept in the inactive state to keep the second word line group at the precharge level.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: A controlling signal generating unit generates a bit line controlling signal, a word line signal, a sense amplifier activating signal, and a column line signal. The bit line controlling signal activates a resetting circuit which resets a bit line. The word line signal controls the connection between a memory cell and the bit line which transmits data to the memory cell. The sense amplifier activating signal activates a sense amplifier which amplifies data transmitted to the bit line. The column line signal activates a column switch which transmits data to the bit line. The controlling signal generating unit activates predetermined signal(s) among the word line signal, the sense amplifier activating signal, the bit line controlling signal, and the column line signal at the start of a write operation. The controlling signal generating unit activates the remaining signal(s) after the acceptance of write data.

Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

Abstract: According to an aspect of the present invention, a memory device having a plurality of banks carries out bank interleaving by use of a plurality of common data buses, the number of which is less than the number of the banks. The present invention enables the data to be read more rapidly while suppressing the increase of the chip area.

Abstract: A semiconductor memory includes p-type MOS transistors (11) dispersed in one-to-one correspondence with sense amplifiers (4−1-4−n) to activate their corresponding sense amplifiers, and a p-type MOS transistor (12) to activate the sense amplifiers (4−1-4−n). After the p-type MOS transistors (11) are overdriven by an external voltage (VCC) higher than a memory stored voltage, the p-type MOS transistor (12) is driven by an internal step-down voltage (VII) that is the memory stored voltage. This increases the driving capability per sense amplifier in comparison with a conventional method and further increases the speed of sense operation in comparison with a simple overdriving method.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: The present invention is a memory circuit having a plurality of word lines, a plurality of bit line pairs, and memory cells disposed at the cross-position thereof. The memory comprises: a sense amplifier which is shared by the first bit line pair and the second bit line pair disposed in the column direction and amplifies a voltage of the bit line pairs; a first and a second bit line transfer gates which are disposed between the sense amplifier and the first and second bit line pairs, and connects the bit line pair at the selected memory cell side to the sense amplifier; a bit line clamper, which is disposed between the first and second bit line transfer gates, is shared by the first bit line pair and the second bit line pair, and supplies the precharge level to the bit line pairs; and a bit line short circuit, which is disposed at the first and the second bit line pairs respectively and shorts the bit line pairs.

Abstract: A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

Abstract: The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.