Abstract: Provided is a non-transitory computer-readable recording medium storing a service management program that causes a computer to execute a process, the process including acquiring a first input load indicating an amount of inputs received by a service at a first point in time, the service being implemented by containers, identifying first numbers of the containers corresponding to the first input load by referring to a storage unit that stores information where a second input load is associated with second numbers of the containers, the second input load indicating an amount of inputs received by the service when a response time of the service is reduced by increasing numbers of the containers to the second numbers of the containers in each of second points in time prior to the first point in time, and increasing the numbers of containers to the first numbers of the containers.

Abstract: A service management device includes a memory, and a processor coupled to the memory and configured to acquire respective execution times of programs that implement a service, identify a first volume having a largest influence on a response time of the service based on the respective execution times of the programs, where the first volume being any one of volumes of a storage device, and at least one of the programs writing and reading data to and from the storage device, and set a priority of writing and reading of data to and from the first volume higher than priorities of writing and reading of data to and from a remaining volume of the volumes.

Abstract: An apparatus includes: a memory and a processor that: obtains, when an operating system detects a first writing process writing first data into a region in a process space in which region a file stored in a storage is mapped, a first size of the first data from information recording a data size of target data for a target address for each of writing processes; reads, when the first size is less than a threshold, a second data corresponding to the first data and having a second size larger than the first size from the file stored in the storage into the memory; rewrites part of the second data stored in a writing region of the second data in the memory with the first data; and writes third data in the writing region into the file stored in the storage, the third data being a result of the rewriting.

Abstract: A service management device includes a memory, and a processor coupled to the memory and configured to acquire respective execution times of programs that implement a service, identify a first volume having a largest influence on a response time of the service based on the respective execution times of the programs, where the first volume being any one of volumes of a storage device, and at least one of the programs writing and reading data to and from the storage device, and set a priority of writing and reading of data to and from the first volume higher than priorities of writing and reading of data to and from a remaining volume of the volumes.

Abstract: An information processing apparatus including: a first management data storing region that stores a plurality of first links being provided one for each of multiple calculating cores and representing an order of migration of pages of a page group allocated to the calculating core among a plurality of the pages; a second management data storing region that stores a second link being provided for an operating system and managing a plurality of pages selected in accordance with the order of migration among the page group of the plurality of first links as a group of candidate pages to be migrated to the second memory; and a migration processor that migrates data of a page selected from the group of the second link from the first memory to the second memory. With this configuration, occurrence of a spinlock is reduced, so that the load on processor is reduced.

Abstract: A storage device includes: a semiconductor memory; and a memory controller coupled to the semiconductor memory and configured to control the semiconductor memory, wherein the memory controller is configured to store information for translating a logical address into a physical address, and execute a dividing process that includes dividing, upon receiving a computational command, the computational command into a plurality of commands based on the information.

Abstract: A memory control apparatus includes a first memory, a second memory, a third memory, and a processor configured to add, to management information, first identification information and information indicating a position where first data is stored when the first data is stored in the first memory, add, to the management information, the first identification information and information indicating a position where second data is stored when the second data is stored in the second memory, add, to the management information, second identification information and information indicating a position where third data is stored when the third data is stored in the third memory, determine which one of the first identification information and the second identification information is associated with fourth data, and perform retrieval of the fourth data from the first memory or the second memory in accordance with information indicating a position where the fourth data is stored.

Abstract: An information processing apparatus includes a memory and a processor and accesses a first storage device and a second storage device wherein an access speed of the second storage device is higher than an access speed of the first storage device. The memory stores information relating to a request in a request from the information processing apparatus to the second storage device. The processor, which is connected to the memory, determines a load on the second storage device based on the information relating to the request.

Abstract: A simulation method executable by a computer that executes a simulation of an instruction execution of a program for a target processor, the method including: setting, to be a predicted result, an execution result of processing a memory access instruction; executing a functional simulation of an instruction execution based on an assumption of the predicted result, and obtaining timing information, so as to calculate an execution time for the memory access instruction in the case of the predicted result; generating and executing a host code; determining a type of memory to be accessed in the memory access instruction; and correcting an execution time for the memory access instruction in the case of the predicted result using a value corresponding to a result of determining the type of the memory, so as to obtain an execution time for the memory access instruction in the functional simulation.

Abstract: A memory stores data, a memory interface circuit reads the data from the memory, and an arithmetic circuit performs a prescribed arithmetic operation on the data. A host interface circuit outputs an arithmetic request to the arithmetic circuit, and also outputs a reading instruction to the memory via the memory interface circuit, upon receipt of an arithmetic instruction from a host device. The host interface circuit receives, from the arithmetic circuit, an arithmetic result of the prescribed arithmetic operation performed on the data read from the memory via the memory interface circuit, and outputs the arithmetic result to the host device.

Abstract: A memory control apparatus includes a first memory, a second memory, a third memory, and a processor configured to add, to management information, first identification information and information indicating a position where first data is stored when the first data is stored in the first memory, add, to the management information, the first identification information and information indicating a position where second data is stored when the second data is stored in the second memory, add, to the management information, second identification information and information indicating a position where third data is stored when the third data is stored in the third memory, determine which one of the first identification information and the second identification information is associated with fourth data, and perform retrieval of the fourth data from the first memory or the second memory in accordance with information indicating a position where the fourth data is stored.

Abstract: A storage device includes: a semiconductor memory; and a memory controller coupled to the semiconductor memory and configured to control the semiconductor memory, wherein the memory controller is configured to store information for translating a logical address into a physical address, and execute a dividing process that includes dividing, upon receiving a computational command, the computational command into a plurality of commands based on the information.

Abstract: A calculating device including; a controller configured to execute, for a multicore processor, a first calculation process of calculating a first performance value of a first code executed by the first core and including a first access instruction by executing a first simulation, a second calculation process of calculating a second performance value of a second code executed by the second core and including a second access instruction by executing a second simulation, a synchronization process of synchronizing the first and the second simulations when the first access instruction is executed in the first simulation, and a correction process of correcting the first performance value, by executing a third simulation to simulate an operation of the cache memory when the first core accesses the main memory through the cache memory in accordance with the first access instruction, after the synchronization by the synchronization process.

Abstract: An information processing apparatus includes a processor configured to perform a data storage process for a first storage area in which the element data having mutually different attributes and included in a row of a matrix are arranged, when a state of the element data stored in the first storage area satisfies a certain condition, specify a column in which the element data having a same attribute are included, and store the element data, read, from the first storage area, the element data having a first attribute, perform a first calculation for the first attribute by using the read element data, read, from the second storage area, the element data included in a column and having the first attribute, perform a second calculation for the first attribute by using the read element data, and perform a calculation process by using a results of the first calculation and the second calculation.

Abstract: An information processing apparatus includes a memory and a processor and accesses a first storage device and a second storage device wherein an access speed of the second storage device is higher than an access speed of the first storage device. The memory stores information relating to a request in a request from the information processing apparatus to the second storage device. The processor, which is connected to the memory, determines a load on the second storage device based on the information relating to the request.

Abstract: A memory stores data, a memory interface circuit reads the data from the memory, and an arithmetic circuit performs a prescribed arithmetic operation on the data. A host interface circuit outputs an arithmetic request to the arithmetic circuit, and also outputs a reading instruction to the memory via the memory interface circuit, upon receipt of an arithmetic instruction from a host device. The host interface circuit receives, from the arithmetic circuit, an arithmetic result of the prescribed arithmetic operation performed on the data read from the memory via the memory interface circuit, and outputs the arithmetic result to the host device.

Abstract: A simulation method executable by a computer that executes a simulation of an instruction execution of a program for a target processor, the method including: setting, to be a predicted result, an execution result of processing a memory access instruction; executing a functional simulation of an instruction execution based on an assumption of the predicted result, and obtaining timing information, so as to calculate an execution time for the memory access instruction in the case of the predicted result; generating and executing a host code; determining a type of memory to be accessed in the memory access instruction; and correcting an execution time for the memory access instruction in the case of the predicted result using a value corresponding to a result of determining the type of the memory, so as to obtain an execution time for the memory access instruction in the functional simulation.

Abstract: A processor emulation device comprising includes an address converter converting a virtual address in a guest environment into a physical address in a host environment, wherein a correspondence between the virtual address and a physical address in the guest environment is different from a correspondence between a virtual address and the physical address in the host environment controlled by a host OS; and an exception handling processing part, in a case where a page attribute obtained in converting the virtual address in the guest environment into the physical address in the guest environment is an attribute specific to the guest environment and absent in the host environment, performing an exception handling process based on the attribute specific to the guest environment.

Abstract: A computing apparatus computes a performance value of a program which includes a specific code which is executed multiple times by the processor and an access instruction for instructing the processor to access a memory area. The computing apparatus includes: a determining unit that determines, whether or not a cache memory is available for use at a time of execution of the access instruction in a simulation of an operation in which the processor executes the program; a generating unit that generates, in a case where the first determining unit has determined that the cache memory is not available, a computational code for computing the performance value of the specific code for a case where the processor executes the specific code, based on performance values of individual instructions within the specific code for a case where the cache memory is not used, without depending on an attribute of the memory area.

Abstract: A simulation apparatus includes a generating circuit configured to detect an internal state of a processor at a start of execution of a process block, when among blocks obtained by dividing code of a program executed by the processor that performs out-of-order execution, processing transitions to the process block in a simulation simulating operation in a case where the processor executes the program, the generating circuit being further configured to generate host code that enables calculation of a block execution period for the case where the processor executes the process block, the generating circuit generating the host code by executing the simulation of the process block based on the detected internal state of the processor; and an executing circuit configured to calculate the block execution period by executing the host code generated by the generating circuit.