Abstract: A processor emulation device comprising includes an address converter converting a virtual address in a guest environment into a physical address in a host environment, wherein a correspondence between the virtual address and a physical address in the guest environment is different from a correspondence between a virtual address and the physical address in the host environment controlled by a host OS; and an exception handling processing part, in a case where a page attribute obtained in converting the virtual address in the guest environment into the physical address in the guest environment is an attribute specific to the guest environment and absent in the host environment, performing an exception handling process based on the attribute specific to the guest environment.

Abstract: A computing apparatus computes a performance value of a program which includes a specific code which is executed multiple times by the processor and an access instruction for instructing the processor to access a memory area. The computing apparatus includes: a determining unit that determines, whether or not a cache memory is available for use at a time of execution of the access instruction in a simulation of an operation in which the processor executes the program; a generating unit that generates, in a case where the first determining unit has determined that the cache memory is not available, a computational code for computing the performance value of the specific code for a case where the processor executes the specific code, based on performance values of individual instructions within the specific code for a case where the cache memory is not used, without depending on an attribute of the memory area.

Abstract: A simulation apparatus includes a generating circuit configured to detect an internal state of a processor at a start of execution of a process block, when among blocks obtained by dividing code of a program executed by the processor that performs out-of-order execution, processing transitions to the process block in a simulation simulating operation in a case where the processor executes the program, the generating circuit being further configured to generate host code that enables calculation of a block execution period for the case where the processor executes the process block, the generating circuit generating the host code by executing the simulation of the process block based on the detected internal state of the processor; and an executing circuit configured to calculate the block execution period by executing the host code generated by the generating circuit.

Abstract: A simulation apparatus includes: operations of: dividing code of a program in a target processor into blocks; setting an execution result of an externally-dependant instruction depending on an external environment as a prediction result; carrying out function simulation based on the prediction result; calculating an execution time of the externally-dependant instruction according to instruction execution timing information and a function simulation result; generating host code which makes a host processor execute performance simulation based on the function simulation result: correcting the execution time of the externally-dependant instruction based on a delay time of the externally-dependent instruction and a execution time of an instruction executed before or after the externally-dependent function if an execution result of the externally-dependent function when the host processor executes the host code differs from the prediction result; and setting a corrected execution time of the external-dependent ins

Abstract: A calculating device including; a controller configured to execute, for a multicore processor, a first calculation process of calculating a first performance value of a first code executed by the first core and including a first access instruction by executing a first simulation, a second calculation process of calculating a second performance value of a second code executed by the second core and including a second access instruction by executing a second simulation, a synchronization process of synchronizing the first and the second simulations when the first access instruction is executed in the first simulation, and a correction process of correcting the first performance value, by executing a third simulation to simulate an operation of the cache memory when the first core accesses the main memory through the cache memory in accordance with the first access instruction, after the synchronization by the synchronization process.

Abstract: An operation of a processor with out-of-order execution is simulated by a computer configured to access a storage unit storing a specific internal state of the processor. A program executed by the processor is divided into a plurality of blocks. When a target block on which an operation simulation is to be performed is changed from a first block to a second block in the plurality of blocks, the computer determines whether the second block is a block that performs a process according to an exception that has occurred in the first block. When it is determined that the second block is a block that performs the process according to the exception, the computer performs the operation simulation of the second block after changing an internal state of the processor in the operation simulation to the specific internal state stored in the storage unit.

Abstract: A correction apparatus includes an acquirer that acquires the execution time of an instruction in a given block among a block group that includes blocks obtained by dividing program code; a detector that detects a first resource group designated by a tail instruction in a preceding block that is executed before the given block and a second resource group designated by a head instruction of the given block; an identifier that identifies a resource common to the first and the second resource groups; a calculator that from the time when the identified resource is used by the head instruction and the time when use of the identified resource by the tail instruction ends, calculates a delay period caused by the preceding block; a corrector that based on the calculated delay period, corrects the acquired execution time; and an output device that outputs the corrected execution time.

Abstract: A computing apparatus computes a performance value of a program which includes a specific code which is executed multiple times by the processor and an access instruction for instructing the processor to access a memory area. The computing apparatus includes: a determining unit that determines, whether or not a cache memory is available for use at a time of execution of the access instruction in a simulation of an operation in which the processor executes the program; a generating unit that generates, in a case where the first determining unit has determined that the cache memory is not available, a computational code for computing the performance value of the specific code for a case where the processor executes the specific code, based on performance values of individual instructions within the specific code for a case where the cache memory is not used, without depending on an attribute of the memory area.

Abstract: A processor emulation device comprising includes an address converter converting a virtual address in a guest environment into a physical address in a host environment, wherein a correspondence between the virtual address and a physical address in the guest environment is different from a correspondence between a virtual address and the physical address in the host environment controlled by a host OS; and an exception handling processing part, in a case where a page attribute obtained in converting the virtual address in the guest environment into the physical address in the guest environment is an attribute specific to the guest environment and absent in the host environment, performing an exception handling process based on the attribute specific to the guest environment.

Abstract: A simulation apparatus includes: operations of: dividing code of a program in a target processor into blocks; setting an execution result of an externally-dependant instruction depending on an external environment as a prediction result; carrying out function simulation based on the prediction result; calculating an execution time of the externally-dependant instruction according to instruction execution timing information and a function simulation result; generating host code which makes a host processor execute performance simulation based on the function simulation result: correcting the execution time of the externally-dependant instruction based on a delay time of the externally-dependent instruction and a execution time of an instruction executed before or after the externally-dependent function if an execution result of the externally-dependent function when the host processor executes the host code differs from the prediction result; and setting a corrected execution time of the external-dependent ins

Abstract: A correction apparatus includes an acquirer that acquires the execution time of an instruction in a given block among a block group that includes blocks obtained by dividing program code; a detector that detects a first resource group designated by a tail instruction in a preceding block that is executed before the given block and a second resource group designated by a head instruction of the given block; an identifier that identifies a resource common to the first and the second resource groups; a calculator that from the time when the identified resource is used by the head instruction and the time when use of the identified resource by the tail instruction ends, calculates a delay period caused by the preceding block; a corrector that based on the calculated delay period, corrects the acquired execution time; and an output device that outputs the corrected execution time.

Abstract: A program, an apparatus and a method verify a program that efficiently verifies a concurrent/parallel program, allowing interactively debugging the current/parallel program. The program causes a computer to execute a detection step that detects the function that has been altered and the function that uses a shared variable influenced by the alteration out of the program to be verified before and after the alteration and also detects the part that is influenced by the alteration, the control structure part and the other parts, a model generation step that generates a model on the basis of the outcome of the detection in the detection step and a verification step that verifies the program to be verified after the alteration by comparing the model of the program to be verified before the alteration and the model of the program to be verified after the alteration.

Abstract: A program, an apparatus and a method verify a program that efficiently verifies a concurrent/parallel program, allowing interactively debugging the current/parallel program. The program causes a computer to execute a detection step that detects the function that has been altered and the function that uses a shared variable influenced by the alteration out of the program to be verified before and after the alteration and also detects the part that is influenced by the alteration, the control structure part and the other parts, a model generation step that generates a model on the basis of the outcome of the detection in the detection step and a verification step that verifies the program to be verified after the alteration by comparing the model of the program to be verified before the alteration and the model of the program to be verified after the alteration.