Patents by Inventor Shinya Nunoue
Shinya Nunoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8729575Abstract: The semiconductor light emitting device according to an embodiment includes an N-type nitride semiconductor layer, a nitride semiconductor active layer disposed on the N-type nitride semiconductor layer, and a P-type nitride semiconductor layer disposed on the active layer. The P-type nitride semiconductor layer includes an aluminum gallium nitride layer. The indium concentration in the aluminum gallium nitride layer is between 1E18 atoms/cm3 and 1E20 atoms/cm3 inclusive. The carbon concentration is equal to or less than 6E17 atoms/cm3. Where the magnesium concentration is denoted by X and the acceptor concentration is denoted by Y, Y>{(?5.35e19)2?(X?2.70e19)2}1/2?4.63e19 holds.Type: GrantFiled: August 23, 2011Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Jongil Hwang, Hung Hung, Yasushi Hattori, Rei Hashimoto, Shinji Saito, Masaki Tohyama, Shinya Nunoue
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Patent number: 8729578Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. The second semiconductor layer is provided on a [0001]-direction side of the first semiconductor layer. The light emitting layer includes a first well layer, a second well layer and a first barrier layer. An In composition ratio of the barrier layer is lower than that of the first well layer and the second well layer. The barrier layer includes a first portion and a second portion. The second portion has a first region and a second region. The first region has a first In composition ratio higher than that of the first portion. The second region is provided between the first region and the first well layer. The second region has a second In composition ratio lower than the first In composition ratio.Type: GrantFiled: March 14, 2013Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shigeya Kimura, Hajime Nago, Koichi Tachibana, Shinya Nunoue
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Patent number: 8728237Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.Type: GrantFiled: September 2, 2010Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
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Publication number: 20140124790Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Toshiki HIKOSAKA, Yoshiyuki HARADA, Hisashi YOSHIDA, Naoharu SUGIYAMA, Shinya NUNOUE
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Publication number: 20140124735Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting portion. The light emitting portion is provided between the semiconductor layers and includes barrier layers and well layers alternately stacked. An n-side end well layer which is closest to the n-type semiconductor layer contains InwnGa1-wnN and has a layer thickness twn. An n-side end barrier layer which is closest to the n-type semiconductor layer contains InbnGa1-bnN and has a layer thickness tbn. A p-side end well layer which is closest to the p-type semiconductor layer contains InwpGa1-wpN and has a layer thickness twp. A p-side end barrier layer which is closest to the p-type semiconductor contains InbpGa1-bpN and has a layer thickness tbp. A value of (wp×twp+bp×tbp)/(twp+tbp) is higher than (wn×twn+bn×tbn)/(twn+tbn) and is not higher than 5 times (wn×twn+bn×tbn)/(twn+tbn).Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi TACHIBANA, Toshiki Hikosaka, Shigeya Kimura, Hajime Nago, Shinya Nunoue
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Publication number: 20140117309Abstract: According to one embodiment, a crystal growth method is disclosed for growing a crystal of a nitride semiconductor on a major surface of a substrate. The major surface is provided with asperities. The method can include depositing a buffer layer on the major surface at a rate of not more than 0.1 micrometers per hour. The buffer layer includes GaxAl1-xN (0.1?x<0.5) and has a thickness of not smaller than 20 nanometers and not larger than 50 nanometers. In addition, the method can include growing the crystal including a nitride semiconductor on the buffer layer at a temperature higher than a temperature of the substrate in the depositing the buffer layer.Type: ApplicationFiled: January 3, 2014Publication date: May 1, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hajime NAGO, Koichi TACHIBANA, Toshiki HIKOSAKA, Shinya NUNOUE
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Publication number: 20140110667Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting portion, a first layer, a second layer, and an intermediate layer. The semiconductor layers include nitride semiconductor. The light emitting portion is provided between the n-type semiconductor layer and the p-type semiconductor layer and includes a quantum well layer. The first layer is provided between the light emitting portion and the p-type semiconductor layer and includes AlX1Ga1-x1N having first Al composition ratio x1. The second layer is provided between the first layer and the p-type semiconductor layer and includes Alx2Ga1-x2N having second Al composition ratio x2 higher than the first Al composition ratio x1. The intermediate layer is provided between the first layer and the light emitting portion and has a thickness not smaller than 3 nanometers and not larger than 8 nanometers and includes Inz1Ga1-z1N (0?z1<1).Type: ApplicationFiled: December 30, 2013Publication date: April 24, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi TACHIBANA, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
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Publication number: 20140111095Abstract: A light-emitting electric-power generation module according to an embodiment includes a photoelectric conversion element for emitting light and generating electric power, a light-emission controller configured to control light emission of the photoelectric conversion element, an electric-power generation controller configured to control electric-power generation of the photoelectric conversion element, and a switching unit configured to switch light-emission state and electric-power generation state of the photoelectric conversion element.Type: ApplicationFiled: April 1, 2013Publication date: April 24, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Rei HASHIMOTO, Jongil Hwang, Shinji Saito, Shinya Nunoue
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Publication number: 20140109831Abstract: According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet.Type: ApplicationFiled: December 30, 2013Publication date: April 24, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiyuki HARADA, Koichi Tachibana, Toshiki Hikosaka, Hajime Nago, Shinya Nunoue
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Patent number: 8704268Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer. The emitting layer is provided between the n-type layer and the p-type layer, and includes a plurality of barrier layers and a plurality of well layers, being alternately stacked. The p-side barrier layer being closest to the p-type layer among the plurality of barrier layer includes a first layer and a second layer, containing group III elements. An In composition ratio in the group III elements of the second layer is higher than an In composition ratio in the group III elements of the first layer. An average In composition ratio of the p-side layer is higher than an average In composition ratio of an n-side barrier layer that is closest to the n-type layer among the plurality of barrier layers.Type: GrantFiled: February 24, 2012Date of Patent: April 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
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Patent number: 8698123Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part. The n-type semiconductor layer includes a nitride semiconductor. The p-type semiconductor layer includes a nitride semiconductor. The light emitting part is provided between the n-type and the p-type semiconductor layers and includes an n-side barrier layer and a first light emitting layer. The first light emitting layer includes a first barrier layer, a first well layer, and a first AlGaN layer. The first barrier layer is provided between the n-side barrier layer and the p-type semiconductor layer. The first well layer contacts the n-side barrier layer between the n-side and the first barrier layer. The first AlGaN layer is provided between the first well layer and the first barrier layer. A peak wavelength ?p of light emitted from the light emitting part is longer than 515 nanometers.Type: GrantFiled: August 19, 2011Date of Patent: April 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8698192Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting part, and a p-side electrode. The light emitting part is provided between the n-type and the p-type semiconductor layers, and includes a plurality of barrier layers and a plurality of well layers. The p-side electrode contacts the p-type semiconductor layer. The p-type semiconductor layer includes first, second, third, and fourth p-type layers. The first p-type layer contacts the p-side electrode. The second p-type layer contacts the light emitting part. The third p-type layer is provided between the first p-type layer and the second p-type layer. The fourth p-type layer is provided between the second p-type layer and the third p-type layer. The second p-type layer contains Al and contains a p-type impurity in a lower concentration lower than that in the first concentration.Type: GrantFiled: August 4, 2011Date of Patent: April 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
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Patent number: 8692287Abstract: According to one embodiment, a nitride semiconductor device includes: a stacked foundation layer, and a functional layer. The stacked foundation layer is formed on an AlN buffer layer formed on a silicon substrate. The stacked foundation layer includes AlN foundation layers and GaN foundation layers being alternately stacked. The functional layer includes a low-concentration part, and a high-concentration part provided on the low-concentration part. A substrate-side GaN foundation layer closest to the silicon substrate among the plurality of GaN foundation layers includes first and second portions, and a third portion provided between the first and second portions. The third portion has a Si concentration not less than 5×1018 cm?3 and has a thickness smaller than a sum of those of the first and second portions.Type: GrantFiled: August 31, 2011Date of Patent: April 8, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomonari Shioda, Hung Hung, Jongil Hwang, Taisuke Sato, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20140084296Abstract: A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)?Wi)/Wi?0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.Type: ApplicationFiled: December 28, 2012Publication date: March 27, 2014Inventors: Hisashi YOSHIDA, Toshiki Hikosaka, Yoshiyuki Harada, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20140084338Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.Type: ApplicationFiled: April 23, 2013Publication date: March 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiyuki HARADA, Toshiki Hikosaka, Hisashi Yoshida, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20140084316Abstract: According to one embodiment, a semiconductor light emitting device includes: a stacked body and an insulative optical path control section. The stacked body includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the light emitting layer are stacked along a stacking direction. The insulative optical path control section penetrates through the second semiconductor layer and the light emitting layer, has a refractive index lower than refractive index of the first semiconductor layer, refractive index of the second semiconductor layer, and refractive index of the light emitting layer. The insulative optical path control section is configured to change traveling direction of light emitted from the light emitting layer.Type: ApplicationFiled: February 28, 2013Publication date: March 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Satoshi MITSUGI, Shinya Nunoue
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Patent number: 8680508Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.Type: GrantFiled: August 31, 2011Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Koichi Tachibana, Hajime Nago, Shinya Nunoue
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Patent number: 8680566Abstract: A semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer formed between the n-type semiconductor layer and the p-type semiconductor layer, and emitting light. The device further includes a p-electrode contacting to the p-type semiconductor layer, and including a first conductive oxide layer having an oxygen content lower than 40 atomic % and a second conductive oxide layer contacting to the first conductive oxide layer and having a higher oxygen content than the oxygen content of the first conductive oxide layer. The device also includes an n-electrode connecting electrically to the n-type semiconductor layer.Type: GrantFiled: December 18, 2012Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Muramoto, Shinya Nunoue
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Patent number: 8680537Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: GrantFiled: September 4, 2012Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 8680548Abstract: A semiconductor light emitting device has a support substrate, a light emitting element, and underfill material. The light emitting element includes a nitride-based group III-V compound semiconductor layer contacted via a bump on the support substrate. The underfill material is disposed between the support substrate and the light emitting element, the underfill material comprising a rib portion disposed outside of an end face of the light emitting element to surround the end surface of the light emitting element.Type: GrantFiled: September 2, 2010Date of Patent: March 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toru Gotoda, Hajime Nago, Toshiyuki Oka, Kotaro Zaima, Shinya Nunoue