Patents by Inventor Shinya Nunoue

Shinya Nunoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8569943
    Abstract: According to one embodiment, the luminescent material emits light having an luminescence peak within a wavelength range of 550 to 590 nm when excited with light having an emission peak in a wavelength range of 250 to 520 nm. The luminescent material has a composition represented by the following formula 1. (Sr1-xEux)aSibAlOcNd??formula 1 wherein x, a, b, c and d satisfy following condition: 0<x?0.16, 0.50?a?0.70, 2.0?b?2.5 0.45?c?1.2, 3.5?d?4.5, and 3.6?d/c?8.0.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Mitsuishi, Naotoshi Matsuda, Yumi Fukuda, Keiko Albessard, Aoi Okada, Masahiro Kato, Ryosuke Hiramatsu, Yasushi Hattori, Shinya Nunoue
  • Patent number: 8564006
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate and a semiconductor functional layer. The substrate is a single crystal. The semiconductor functional layer is provided on a major surface of the substrate and includes a nitride semiconductor. The substrate includes a plurality of structural bodies disposed in the major surface. Each of the plurality of structural bodies is a protrusion provided on the major surface or a recess provided on the major surface. An absolute value of an angle between a nearest direction of an arrangement of the plurality of structural bodies and a nearest direction of a crystal lattice of the substrate in a plane parallel to the major surface is not less than 1 degree and not more than 10 degrees.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: October 22, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hisashi Yoshida, Hiroshi Ono, Hajime Nago, Yoshiyuki Harada, Toshiki Hikosaka, Maki Sugai, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 8558251
    Abstract: A light emitting device according to one embodiment includes a board; plural first light emitting elements mounted on the board to emit light having a wavelength of 250 nm to 500 nm; plural second light emitting elements mounted on the board to emit light having a wavelength of 250 nm to 500 nm; a first fluorescent layer formed on each of the first light emitting elements, the first fluorescent layer including a first phosphor; and a second fluorescent layer formed on each of the second light emitting elements, the second fluorescent layer including a second phosphor. The second phosphor is higher than the first phosphor in luminous efficiency at 50° C., and is lower than the first phosphor in the luminous efficiency at 150° C.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Mitsuishi, Yumi Fukuda, Aoi Okada, Ryosuke Hiramatsu, Naotoshi Matsuda, Shinya Nunoue, Keiko Albessard, Masahiro Kato
  • Patent number: 8546824
    Abstract: A light emitting device according to one embodiment includes: a board; plural first light emitting units each including a first light emitting element and a first fluorescent layer formed on the first light emitting element having a green phosphor; plural second light emitting units each including a second light emitting element and a second fluorescent layer formed on the second light emitting element having a red phosphor; the second fluorescent layers and the first fluorescent layers being separated in a non-contact manner with gas interposed there between; and plural third light emitting units each including a third light emitting element and a resin layer formed on the third light emitting element having neither a green phosphor nor the red phosphor, the third light emitting units being disposed between the first light emitting units and the second light emitting units.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: October 1, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Iwao Mitsuishi, Yumi Fukuda, Aoi Okada, Naotoshi Matsuda, Shinya Nunoue, Keiko Albessard, Masahiro Kato
  • Publication number: 20130248921
    Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first electrode, and a second electrode. The stacked structural body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting portion. The stacked structural body has a first major surface on a side of the second semiconductor layer. The first electrode is provided on the first semiconductor. The second electrode is provided on the second semiconductor layer. The first electrode includes a first pad portion and a first extending portion that extends from the first pad portion along a first extending direction. The first extending portion includes a first width-increasing portion. A width of the first width-increasing portion along a direction orthogonal to the first extending direction is increased from the first pad portion toward an end of the first extending portion.
    Type: Application
    Filed: May 13, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeya KIMURA, Taisuke SATO, Toshihide ITO, Toshiyuki OKA, Shinya NUNOUE
  • Publication number: 20130244360
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor light emitting element. The method can include bonding a stacked main body of a structural body to a substrate main body. The structural body includes a growth substrate and the stacked main body provided on the growth substrate. The stacked main body includes a first nitride semiconductor film, a light emitting film provided on the first nitride semiconductor film, and a second nitride semiconductor film provided on the light emitting film. The method can include removing the growth substrate. The method can include forming a plurality of stacked bodies. The method can include forming an uneven portion in a surface of a first nitride semiconductor layer. The method can include forming a plurality of the semiconductor light emitting elements.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 19, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Taisuke SATO, Kotaro Zaima, Jumpei Tajima, Naoharu Sugiyama, Shinya Nunoue
  • Publication number: 20130234182
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer, a bonding pad, a narrow wire electrode and a first insulating layer. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer and is in contact with the first semiconductor layer. The narrow wire electrode includes a first portion and a second portion. The first portion is provided on a surface of the first semiconductor layer not in contact with the light emitting layer and is in ohmic contact with the first semiconductor layer. The second portion is provided on the surface and located between the first portion and the bonding pad. The narrow wire electrode is electrically connected to the bonding pad. The first insulating layer is provided between the second portion and the first semiconductor layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi KATSUNO, Satoshi Mitsugi, Shinya Nunoue
  • Publication number: 20130234106
    Abstract: According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Taisuke Sato, Kotaro Zaima, Jumpei Tajima, Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Shinya Nunoue
  • Publication number: 20130234298
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes a placement step and a bonding step. The placement step faces a semiconductor active portion toward a support substrate portion via a bonding portion disposed between the semiconductor active portion and the support substrate portion. The bonding portion includes a bonding layer and a light absorption layer, absorptance of the light absorption layer for laser light being higher than or equal to absorptance of the bonding layer for the laser light. The bonding step bonds the semiconductor active portion and the support substrate portion by irradiating the light absorption layer with the laser light through the support substrate portion and melting the bonding layer by thermal conduction from the light absorption layer heated by the laser light.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi MITSUGI, Toshiyuki OKA, Shinya NUNOUE, Hiroshi KATSUNO
  • Publication number: 20130234178
    Abstract: According to one embodiment, a semiconductor light emitting device includes a silicon substrate, a buffer layer, a foundation semiconductor layer, a first semiconductor layer, a light emitting unit and a second semiconductor layer. The buffer layer is provided on a part of a major surface of the silicon substrate. The foundation semiconductor layer is crystal-grown from an upper surface of the buffer layer, covers a non-formed region of the major surface where the buffer layer is not provided, and is spaced apart from the non-formed region. The first semiconductor layer is provided on the foundation semiconductor layer and has a first conductivity type. The light emitting unit is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting unit and has a second conductivity type.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Mitsugi, Naoharu Sugiyama, Taisuke Sato, Shinya Nunoue
  • Publication number: 20130234151
    Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.
    Type: Application
    Filed: September 4, 2012
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiki HIKOSAKA, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
  • Publication number: 20130237036
    Abstract: According to one embodiment, a method for manufacturing a nitride semiconductor layer is disclosed. The method can include forming a first lower layer on a major surface of a substrate and forming a first upper layer on the first lower layer. The first lower layer has a first lattice spacing along a first axis parallel to the major surface. The first upper layer has a second lattice spacing along the first axis larger than the first lattice spacing. At least a part of the first upper layer has compressive strain. A ratio of a difference between the first and second lattice spacing to the first lattice spacing is not less than 0.005 and not more than 0.019. A growth rate of the first upper layer in a direction parallel to the major surface is larger than that in a direction perpendicular to the major surface.
    Type: Application
    Filed: September 5, 2012
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiki HIKOSAKA, Yoshiyuki HARADA, Hisashi YOSHIDA, Naoharu SUGIYAMA, Shinya NUNOUE
  • Publication number: 20130234155
    Abstract: A semiconductor device of an embodiment includes: a semiconductor layer made of p-type nitride semiconductor; an oxide layer formed on the semiconductor layer, the oxide layer being made of a crystalline nickel oxide, and the oxide layer having a thickness of 3 nm or less; and a metal layer formed on the oxide layer.
    Type: Application
    Filed: April 26, 2013
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Maki Sugai, Eiji Muramoto, Shinya Nunoue
  • Publication number: 20130229106
    Abstract: According to one embodiment, the luminescent material emits light having an luminescence peak within a wavelength range of 550 to 590 nm when excited with light having an emission peak in a wavelength range of 250 to 520 nm. The luminescent material has a composition represented by the following formula 1. (Sr1-xEux)aSibAlOcNd??formula 1 wherein x, a, b, c and d satisfy following condition: 0<x?0.16, 0.50?a?0.70, 2.0?b?2.5 0.45?c?1.2, 3.5?d?4.5, and 3.6?d/c?8.0.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 5, 2013
    Inventors: Iwao MITSUISHI, Naotoshi MATSUDA, Yumi FUKUDA, Keiko ALBESSARD, Aoi OKADA, Masahiro KATO, Ryosuke HIRAMATSU, Yasushi HATTORI, Shinya NUNOUE
  • Publication number: 20130228745
    Abstract: According to one embodiment, a nitride semiconductor device includes a first layer and a functional layer. The first layer is formed on an amorphous layer, includes aluminum nitride, and has a compressive strain or a tensile strain. The functional layer is formed on the first layer and includes a nitride semiconductor.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi ONO, Tomonari Shioda, Naoharu Sugiyama, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 8526477
    Abstract: A semiconductor light emitting device of one embodiment includes: a substrate; an n-type layer of an n-type nitride semiconductor on the substrate; an active layer of a nitride semiconductor on the n-type semiconductor layer; a p-type layer of a p-type nitride semiconductor on the active layer. The p-type layer has a ridge stripe shape. The device has an end-face layer of a nitride semiconductor formed on an end face of the n-type semiconductor layer, the active layer, and the p-type semiconductor layer. The end face is perpendicular to an extension direction of the ridge stripe shape. The end-face layer has band gap wider than the active layer. The end-face layer has Mg concentration in the range of 5E16 atoms/cm3 to 5E17 atoms/cm3 at a region adjacent to the p-type layer.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Jongil Hwang, Shinya Nunoue
  • Patent number: 8525197
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part provided therebetween. The light emitting part includes a plurality of light emitting layers. Each of the light emitting layers includes a well layer region and a non-well layer region which is juxtaposed with the well layer region in a plane perpendicular to a first direction from the n-type semiconductor layer towards the p-type semiconductor layer. Each of the well layer regions has a common An In composition ratio. Each of the well layer regions includes a portion having a width in a direction perpendicular to the first direction of 50 nanometers or more.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Harada, Toshiki Hikosaka, Tomonari Shioda, Koichi Tachibana, Hajime Nago, Shinya Nunoue
  • Patent number: 8525195
    Abstract: According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers, a light emitting portion, a multilayered structural body, and an n-side intermediate layer. The light emitting portion is provided between the semiconductor layers. The light emitting portion includes barrier layers containing GaN, and a well layer provided between the barrier layers. The well layer contains Inx1Ga1-x1N. The body is provided between the n-type semiconductor layer and the light emitting portion. The body includes: first layers containing GaN, and a second layer provided between the first layers. The second layer contains Inx2Ga1-x2N. Second In composition ratio x2 is not less than 0.6 times of first In composition ratio x1 and is lower than the first In composition x1. The intermediate layer is provided between the body and the light emitting portion and includes a third layer containing Aly1Ga1-y1N (0<y1?0.01).
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Nago, Koichi Tachibana, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8525194
    Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Hung Hung, Jongil Hwang, Taisuke Sato, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8525203
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting portion, a first layer, a second layer, and an intermediate layer. The semiconductor layers include nitride semiconductor. The light emitting portion is provided between the n-type semiconductor layer and the p-type semiconductor layer and includes a quantum well layer. The first layer is provided between the light emitting portion and the p-type semiconductor layer and includes AlX1Ga1-x1N having first Al composition ratio x1. The second layer is provided between the first layer and the p-type semiconductor layer and includes Alx2Ga1-x2N having second Al composition ratio x2 higher than the first Al composition ratio x1. The intermediate layer is provided between the first layer and the light emitting portion and has a thickness not smaller than 3 nanometers and not larger than 8 nanometers and includes Inz1Ga1-z1N (0?z1<1).
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue