Patents by Inventor Shinya Sasagawa

Shinya Sasagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147761
    Abstract: A method for manufacturing a display apparatus with high display quality is provided. The method is for manufacturing a display apparatus including first to third insulators, first and second conductors, and a first EL layer. The first conductor is formed over the first insulator, and the second insulator is formed over the first insulator and over the first conductor. Next, a first opening portion reaching the first conductor is formed in a region of the second insulator overlapping with the first conductor. A positive photoresist is applied to regions over the first and second insulators and over the first conductor, and a second opening portion with an inversely tapered structure reaching the first conductor and the second insulator is formed in a region of the photoresist overlapping with the first opening portion and the first conductor.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 2, 2024
    Inventors: Yuichi YANAGISAWA, Shinya SASAGAWA, Shiro NISHIZAKI, Ryota HODO
  • Publication number: 20240138204
    Abstract: A high-definition and high-resolution display apparatus is provided. A conductive film, a first layer, and a first sacrificial layer are formed. The first layer and the first sacrificial layer are processed to expose part of the conductive film. A second layer and a second sacrificial layer are formed over the first sacrificial layer and the conductive film. The second layer and the second sacrificial layer are processed to expose part of the conductive film. The conductive film is processed to form a first pixel electrode overlapping with the first sacrificial layer and a second pixel electrode overlapping with the second sacrificial layer. Two insulating films covering at least a side surface of the first pixel electrode, a side surface of the second pixel electrode, a side surface of the first layer, a side surface of the second layer, a side surface and a top surface of the first sacrificial layer, and a side surface and atop surface of the second sacrificial layer are formed.
    Type: Application
    Filed: February 24, 2022
    Publication date: April 25, 2024
    Inventors: Ryota HODO, Shinya SASAGAWA, Yoshikazu HIURA, Takahiro FUJIE
  • Publication number: 20240122052
    Abstract: A novel display panel that is highly convenient, useful, or reliable is provided. The display panel includes a first light-emitting device, a second light-emitting device, a partition, a first protective layer, and a second protective layer. The first light-emitting device includes a first electrode, a second electrode, and a first layer, and the first layer is interposed between the electrodes. The first layer includes a first material having a hole-transport property and a first substance having an electron-accepting property, and the first protective layer is in contact with the second electrode. The second light-emitting device includes a third electrode, a fourth electrode, and a second layer, and the second layer is interposed between the electrodes. The second layer includes the first material having a hole-transport property and the first substance having an electron-accepting property, and the second layer includes a first gap between the second layer and the first layer.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 11, 2024
    Inventors: Shinya SASAGAWA, Ryota HODO, Yoshikazu HIURA, Takahiro FUJIE
  • Patent number: 11935944
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 11929416
    Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a first insulator over the second oxide, a first conductor over the first insulator, and a second conductor and a third conductor over the second oxide. The second conductor includes a first region and a second region, the third conductor includes a third region and a fourth region, the second region is positioned above the first region, the fourth region is positioned above the third region, and each of the second conductor and the third conductor contains tantalum and nitrogen. The atomic ratio of nitrogen to tantalum in the first region is higher than the atomic ratio of nitrogen to tantalum in the second region, and the atomic ratio of nitrogen to tantalum in the third region is higher than the atomic ratio of nitrogen to tantalum in the fourth region.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: March 12, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ryo Tokumaru, Shinya Sasagawa, Tomonori Nakayama
  • Publication number: 20240074240
    Abstract: A high-resolution or high-definition display device is provided.
    Type: Application
    Filed: January 18, 2022
    Publication date: February 29, 2024
    Inventors: Ryota HODO, Shinya SASAGAWA, Yoshikazu HIURA, Takahiro FUJIE, Shunpei YAMAZAKI
  • Publication number: 20240063028
    Abstract: A semiconductor device in which variation in characteristics is small is provided. A first insulator is formed; a first insulator is formed; a conductor is formed over the first insulator; a second insulator is formed over the conductor; a third insulator is formed over the second insulator; an oxide is formed over the third insulator; first heat treatment is performed; and second heat treatment following the first heat treatment is performed. The temperature of the first heat treatment is lower than the temperature of the second heat treatment.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 22, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shunichi ITO, Yoshihiro KAMATSU, Shinobu KAWAGUCHI, Shinya SASAGAWA
  • Publication number: 20240057403
    Abstract: A highly reliable display device is provided. The display device includes a transistor over a substrate, a first insulating layer over the transistor, a second insulating layer over the first insulating layer, a plug placed to be embedded in the first insulating layer and the second insulating layer, and a light-emitting element over the second insulating layer. The light-emitting element includes a first conductive layer, an EL layer over the first conductive layer, and a second conductive layer over the EL layer. The plug electrically connects one of a source and a drain of the transistor to the first conductive layer. The second insulating layer has higher capability of inhibiting hydrogen diffusion than the first insulating layer.
    Type: Application
    Filed: December 16, 2021
    Publication date: February 15, 2024
    Inventors: Yuichi YANAGISAWA, Shinya SASAGAWA, Takashi HAMADA
  • Patent number: 11901372
    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: February 13, 2024
    Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
  • Publication number: 20240049562
    Abstract: A display device with high resolution is provided. The display device includes a first conductor, a first insulator over the first conductor, a second conductor provided inside an opening of the first insulator, a first light-emitting layer in contact with a top surface of the second conductor and a top surface of the first insulator, and a third conductor in contact with a top surface of the first light-emitting layer.
    Type: Application
    Filed: December 6, 2021
    Publication date: February 8, 2024
    Inventors: Yuichi YANAGISAWA, Shinya SASAGAWA, Takashi HAMADA
  • Publication number: 20230402279
    Abstract: A semiconductor device in which variation in electrical characteristics is small is provided. A first insulator is deposited, a metal oxide is device over the first insulator, a second insulator is device over the metal oxide, an oxide film is device over the second insulator, and heat treatment is performed, whereby hydrogen in the first insulator, the second insulator, and the oxide is transferred and absorbed into the metal oxide. The metal oxide is formed by an ALD method.
    Type: Application
    Filed: August 6, 2021
    Publication date: December 14, 2023
    Inventors: Shunpei YAMAZAKI, Yoshihiro KOMATSU, Toshikazu OHNO, Yuichi YANAGISAWA, Shinya SASAGAWA
  • Patent number: 11791201
    Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: October 17, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Yuta Iida, Satoru Okamoto
  • Patent number: 11776966
    Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: October 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Hodo, Motomu Kurata, Shinya Sasagawa, Satoru Okamoto, Shunpei Yamazaki
  • Publication number: 20230307550
    Abstract: A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes a first device layer to an n-th (n is a natural number of 2 or more) device layer, each of which includes a first barrier insulating film, a second barrier insulating film, a third barrier insulating film, an oxide semiconductor device, a first conductor, and a second conductor.
    Type: Application
    Filed: August 17, 2021
    Publication date: September 28, 2023
    Inventors: Shunpei YAMAZAKI, Yasumasa YAMANE, Yoshinori ANDO, Shigeki KOMORI, Ryota HODO, Tatsuya ONUKI, Shinya SASAGAWA
  • Publication number: 20230262952
    Abstract: A semiconductor device with a small variation in transistor characteristics can be provided. A step of forming an opening in a structure body including an oxide semiconductor device to reach the oxide semiconductor device, a step of embedding a first conductor in the opening, a step of forming a second conductor in contact with a top surface of the first conductor, a step of forming a first barrier insulating film by a sputtering method to cover the structure body, the first conductor, and the second conductor, and a step of forming a second barrier insulating film over the first barrier insulating film by an ALD method are included. The first barrier insulating film and the second barrier insulating film each have a function of inhibiting hydrogen diffusion.
    Type: Application
    Filed: August 5, 2021
    Publication date: August 17, 2023
    Inventors: Shunpei YAMAZAKI, Motomu KURATA, Tsutomu MURAKAWA, Ryo ARASAWA, Kunihiro FUKUSHIMA, Yasumasa YAMANE, Shinya SASAGAWA
  • Publication number: 20230230979
    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
    Type: Application
    Filed: March 23, 2023
    Publication date: July 20, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
  • Publication number: 20230200198
    Abstract: To provide a light-emitting element in which an organic compound layer can be processed at once by a photolithography technique. A first electrode and an organic compound layer including an electron-injection layer are formed over an insulating surface. The electron-injection layer is the outermost layer of the organic compound layer and contains an organic compound having a basic skeleton and an acid dissociation constant pKa of greater than or equal to 1. A sacrificial layer and a mask are formed over the electron-injection layer and the sacrificial layer is processed into an island shape using the mask. With use of the island-shaped sacrificial layer as a mask, the organic compound layer is processed into an island shape to cover the first electrode. Part of the island-shaped sacrificial layer is removed with an acidic chemical solution to expose the electron-injection layer. A second electrode is formed to cover the electron-injection layer.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 22, 2023
    Inventors: Shunpei YAMAZAKI, Sachiko KAWAKAMI, Nobuharu OHSAWA, Yuji IWAKI, Ryota HODO, Kentaro SUGAYA, Shinya SASAGAWA, Takahiro FUJIE, Yoshikazu HIURA, Toshiki SASAKI, Takeyoshi WATABE, Kunihiko SUZUKI
  • Publication number: 20230132598
    Abstract: A semiconductor device in which variations in characteristics, deterioration of elements, and abnormality in shape are inhibited is provided. The semiconductor device includes a first region including a plurality of elements and a second region including a plurality of dummy elements. The second region is provided in an outer edge of the first region, and the element and the dummy element each include an oxide semiconductor. The element and the dummy element have the same structure, and a structure body included in the element and a structure body included in the dummy element are formed with the same material and provided in the same layer. The oxide semiconductor includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 4, 2023
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Shinya SASAGAWA, Erika TAKAHASHI, Katsuaki TOCHIBAYASHI, Ryo ARASAWA
  • Publication number: 20230113593
    Abstract: A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.
    Type: Application
    Filed: March 19, 2021
    Publication date: April 13, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshihiro KOMATSU, Shota MIZUKAMI, Shinobu KAWAGUCHI, Hiromi SAWAI, Yasumasa YAMANE, Yuji EGI, Yujiro SAKURADA, Shinya SASAGAWA
  • Patent number: 11616085
    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: March 28, 2023
    Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki