Patents by Inventor Shinya Sasagawa

Shinya Sasagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10304864
    Abstract: To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Okazaki, Tomoaki Moriwaka, Shinya Sasagawa, Takashi Ohtsuki
  • Publication number: 20190115478
    Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 18, 2019
    Inventors: Shinya SASAGAWA, Motomu KURATA, Satoru OKAMOTO, Shunpei YAMAZAKI
  • Patent number: 10256348
    Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hideomi Suzawa, Kazuya Hanaoka, Shinya Sasagawa, Satoru Okamoto
  • Publication number: 20190103478
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Application
    Filed: November 19, 2018
    Publication date: April 4, 2019
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Shinya SASAGAWA, Motomu KURATA, Masashi TSUBUKU
  • Patent number: 10229906
    Abstract: Provided is a semiconductor device that occupies a small area, a highly integrated semiconductor device, or a semiconductor device with high productivity. To fabricate an integrated circuit, a first insulating film is formed over a p-channel transistor; a transistor including an oxide semiconductor is formed over the first insulating film; a second insulating film is formed over the transistor; an opening, that is, a contact hole part of a sidewall of which is formed of the oxide semiconductor of the transistor, is formed in the first insulating film and the second insulating film; and an electrode connecting the p-channel transistor and the transistor including an oxide semiconductor to each other is formed.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Shinya Sasagawa
  • Patent number: 10224433
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
  • Patent number: 10211240
    Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 10199508
    Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: February 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Yutaka Okazaki, Motomu Kurata, Katsuaki Tochibayashi, Shinya Sasagawa, Kensuke Yoshizumi, Hideomi Suzawa
  • Patent number: 10181531
    Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Satoru Okamoto, Shunpei Yamazaki
  • Patent number: 10164120
    Abstract: A transistor including a semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator is manufactured by forming a hard mask layer including a fourth conductor over the second insulator, a third insulator over the fourth conductor, forming an opening portion in the second insulator with the hard mask layer as the mask, eliminating the hard mask layer by forming the opening portion, and forming the first insulator and the first conductor in the opening portion.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: December 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Katsuaki Tochibayashi, Satoru Okamoto, Akihisa Shimomura
  • Patent number: 10153375
    Abstract: A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: December 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Patent number: 10141452
    Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
  • Patent number: 10134879
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 10079295
    Abstract: A method for manufacturing an oxide semiconductor layer, comprising forming an oxide semiconductor layer over an insulating layer so as to be along with a curved surface of a projecting structural body of the insulating layer, wherein a length of the projecting structural body in a height direction is larger than a width of the projecting structural body, is provided.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: September 18, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki, Shinya Sasagawa, Akihiro Ishizuka
  • Publication number: 20180248010
    Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 30, 2018
    Inventors: Yuta ENDO, Hideomi SUZAWA, Kazuya HANAOKA, Shinya SASAGAWA, Satoru OKAMOTO
  • Publication number: 20180248043
    Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 30, 2018
    Inventors: Yoshinobu Asami, Yutaka Okazaki, Satoru Okamoto, Shinya Sasagawa
  • Patent number: 10050062
    Abstract: A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. A contact plug penetrates the first insulating layer, the conductive layer, and the second insulating layer. In a depth direction from the second insulating layer to the first insulating layer, a diameter of the contact plug changes to a smaller value at an interface between the second insulating layer and the conductive layer.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: August 14, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Hidekazu Miyairi, Shunpei Yamazaki, Motomu Kurata
  • Patent number: 10043914
    Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Taiga Muraoka, Hiroaki Honda, Takashi Hamada
  • Publication number: 20180197997
    Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 12, 2018
    Inventors: Daigo ITO, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
  • Patent number: 10008587
    Abstract: A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Atsuo Isobe, Toshihiko Saito, Takehisa Hatano, Hideomi Suzawa, Shinya Sasagawa, Junichi Koezuka, Yuichi Sato, Shinji Ohno