Patents by Inventor Shinya Tanaka

Shinya Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140014951
    Abstract: A semiconductor device (100A) according to the present invention includes: an oxide semiconductor layer (4) having a first contact region (4a) and a second contact region (4b) and a channel region (4c) located between the first contact region (4a) and the second contact region (4b); a source electrode (5) formed on the oxide semiconductor layer (4) so as to be in contact with the first contact region (4a); and a drain electrode (6) formed on the oxide semiconductor layer (4) so as to be in contact with the second contact region (4b). All side faces of the oxide semiconductor layer (4) are located over the gate electrode (2); a width of the source electrode (5) is greater than a width of the oxide semiconductor layer (4); and a width of the drain electrode (6) is greater than a width of the oxide semiconductor layer (4).
    Type: Application
    Filed: January 5, 2012
    Publication date: January 16, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shingo Kawashima, Yukinobu Nakata, Atsuhito Murai, Shinya Tanaka
  • Publication number: 20140010562
    Abstract: An image forming apparatus includes a transfer member configured to abut against an image carrier for carrying a toner image to form a transfer nip; and a power supply configured to output a bias voltage for transferring the toner image on the image carrier onto a recording medium nipped in the transfer nip. The bias voltage includes a first voltage for transferring the toner image from the image carrier onto the recording medium in a transfer direction and a second voltage having an opposite polarity of the first voltage, the first and the second voltages being alternately output. A time-averaged value of the bias voltage is set to a polarity in the transfer direction and is set in the transfer direction side with respect to a median between a maximum and a minimum of the bias voltage.
    Type: Application
    Filed: March 16, 2012
    Publication date: January 9, 2014
    Inventors: Shinya Tanaka, Naomi Sugimoto, Haruo Iimura, Shinji Aoki, Yasuhiko Ogino
  • Publication number: 20130322688
    Abstract: A periodic stationary object detection system extracts a feature point of a three-dimensional object from image data on a predetermined region of a bird's eye view image for each of multiple sub regions included in the predetermined region, calculates waveform data corresponding to a distribution of the feature points in the predetermined region on the bird's eye view image, and judges whether or not the three-dimensional object having the extracted feature point is a periodic stationary object candidate on the basis of whether or not peak information of the waveform data is equal to or larger than a predetermined threshold value.
    Type: Application
    Filed: February 17, 2012
    Publication date: December 5, 2013
    Inventors: Chikao Tsuchiya, Yasuhisa Hayakawa, Shinya Tanaka, Hiroyuki Furushou, Osamu Fukata
  • Publication number: 20130308968
    Abstract: An image forming apparatus includes a transfer bias output device and an information receiving device. The transfer bias output device outputs a transfer bias including a superimposed bias composed of an AC bias superimposed on a DC bias to form a transfer electric field in a transfer nip between an image bearing member bearing a toner image and a nip forming member, to transfer the toner image onto a recording medium in the transfer nip. A controller operatively connected to the information receiving device and the transfer bias output device causes the transfer bias output device to change a target output of a peak-to-peak voltage of the AC bias based on information received by the information receiving device that affects transfer of the toner image and to reduce a target output of the DC bias as the target output value of the peak-to-peak voltage of the AC bias increases.
    Type: Application
    Filed: May 14, 2013
    Publication date: November 21, 2013
    Inventors: Shinya TANAKA, Hirokazu Ishii, Yasunobu Shimizu, Keigo Nakamura
  • Patent number: 8586987
    Abstract: A second stem wires (17c), formed by a reflective pixel electrode layer formed as a different layer from first stem wires (17a), is provided in such a way as to extend along a long side of its adjacent one of the first stem wires (17a). This makes it possible to achieve a TFT array substrate (1) on which a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) have been monolithically formed, wherein the width of a frame part in which the a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) are formed can be reduced.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: November 19, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Kikuchi, Shinya Tanaka, Junya Shimada, Chikao Yamasaki
  • Patent number: 8581257
    Abstract: The circuit board (1) of the present invention includes a plurality of transistor elements provided on a single insulating substrate (2) for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT (10) having a channel layer (11) formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT (20) having a channel layer (21) formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT (10) and the a-Si TFT (20) is a bottom-gate transistor.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: November 12, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsuhito Murai, Shinya Tanaka, Hideki Kitagawa, Hajime Imai, Mitsunori Imade, Tetsuo Kikuchi, Kazunori Morimoto, Junya Shimada, Jun Nishimura
  • Patent number: 8575620
    Abstract: The present invention provides a circuit board with a reduced circuit area, and a display device comprising the circuit board and a narrower picture frame. The circuit board of the present invention comprises: a bottom gate thin film transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and a top gate thin film transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor layer and the second semiconductor layer are formed from the same material, and the first drain electrode or the first source electrode and the second gate electrode are connected without interposing any other thin film transistor therebetween, and have the same electric potential.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 5, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Chikao Yamasaki, Shinya Tanaka, Tetsuo Kikuchi, Junya Shimada
  • Patent number: 8559588
    Abstract: Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.
    Type: Grant
    Filed: December 25, 2009
    Date of Patent: October 15, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Kikuchi, Shinya Tanaka, Chikao Yamasaki, Junya Shimada
  • Publication number: 20130252459
    Abstract: A connection structure of an electric wire and a terminal includes the electric wire, the terminal, and a seal part. The electric wire has an insulating coated part in which a conductor part is covered with an insulating material, and a conductor exposed part in which the insulating material of an end of the electric wire is removed. The terminal includes a first crimp part crimped to the insulating coated part, and a second crimp part crimped to the conductor exposed part. The seal part is made of thermoplastic elastomer and covers a surface including the first crimp part and the insulating coated part of a side extending from said first crimp part toward a direction opposite to the end of the electric wire and a surface of the second crimp part in an extension direction of the electric wire.
    Type: Application
    Filed: May 15, 2013
    Publication date: September 26, 2013
    Applicant: YAZAKI CORPORATION
    Inventors: Shinya TANAKA, Hisashi HANAZAKI, Hironori KITAGAWA
  • Publication number: 20130242102
    Abstract: A driving assistance device includes a camera, a moving object detector, a candidate reflection region detector, a predetermined position brightness detector and a cause determiner. The moving object detector and the candidate reflection region detector sets a detection region for detecting, from image data captured by the camera, existence of an adjacent vehicle in an adjacent lane. The predetermined position brightness detector detects a candidate light projecting object which projects light with brightness equal to or higher than a predetermined threshold value. The cause determiner determines whether or not there exists a candidate light projecting object which indicates existence of the adjacent vehicle in the detection region.
    Type: Application
    Filed: April 11, 2012
    Publication date: September 19, 2013
    Inventors: Chikao Tsuchiya, Yasuhisa Hayakawa, Shinya Tanaka, Osamu Fukata
  • Patent number: 8536469
    Abstract: A body composition monitor of the present invention includes means for inputting a reference value of a body composition component, means for inputting a measurement value of the body composition component, body composition comparison means for comparing the reference value and the measurement value so as to determine a body composition component change amount of the measurement value relative to the reference value, display means provided with a plurality of stages for displaying one of the stages corresponding to the body composition component change amount, and stage determination means provided with a plurality of determination widths respectively corresponding to the plurality of stages for determining one of the stages corresponding to the body composition component change amount with using the plurality of determination widths, wherein the plurality of determination widths are not identical to each other.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: September 17, 2013
    Assignee: Omron Healthcare Co., Ltd
    Inventors: Tetsuya Sato, Yumi Kitamura, Shinya Tanaka
  • Patent number: 8534836
    Abstract: When pattern recognition of a fundus image is started in step S1, output from a fundus image sensing unit is compared with a regional pattern of stored fundus image specific regions in step S2, and it is decided whether to proceed to pattern recognition. If pattern recognition is possible, based on an AF evaluation value, the lens is driven, with which automatic focusing is completed.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: September 17, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Inoue, Shinya Tanaka, Hiroshi Aoki
  • Patent number: 8536470
    Abstract: A body composition monitor of the present invention includes means for measuring a body composition, means for storing a measured body composition value, and body composition comparison means for comparing the measured body composition value and a stored body composition value, in which the body composition monitor further includes means for inputting a body weight value, means for storing an inputted body weight, body weight comparison means for comparing the inputted body weight and stored body weight, body composition change determination means for determining a change degree of the body composition value with using a comparison result of the body composition comparison means and a comparison result of the body weight comparison means, and display means for displaying a determination result determined by the body composition change determination means.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: September 17, 2013
    Assignee: Omron Healthcare Co., Ltd.
    Inventors: Tetsuya Sato, Shinya Tanaka, Yumi Kitamura
  • Publication number: 20130236201
    Abstract: An image forming apparatus includes a toner forced consumption control unit that performs toner forced consumption control in which toner in a developing unit is forcibly consumed when a certain condition to perform the toner forced consumption control is met. The certain condition to perform the toner forced consumption control includes a specific performance condition that a transfer bias switching condition to switch a transfer bias to a superimposed transfer bias in which an alternating current component is superimposed on a direct current component, from a direct current transfer bias is met. When the specific performance condition is met, the toner forced consumption control unit performs preliminary toner forced consumption control in which the toner forced consumption control is performed before an image forming operation using the superimposed transfer bias is started.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 12, 2013
    Inventors: Takehide Mizutani, Shinya Tanaka, Yasunobu Shimizu, Hirokazu Ishii, Keigo Nakamura
  • Patent number: 8531224
    Abstract: An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver. In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: September 10, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akihisa Iwamoto, Hideki Morii, Takayuki Mizunaga, Shinya Tanaka, Tetsuo Kikuchi, Takaharu Yamada, Satoshi Horiuchi, Chikao Yamasaki, Kei Ikuta
  • Patent number: 8523356
    Abstract: A fundus camera includes an irradiation unit including a plurality of LED elements and a fluorescent material that emits light by being excited by light emitted from the LED elements and configured to emit light that is generated by combining light emitted from the LED elements and excitation light from the fluorescent material, an illumination optical system configured to irradiate an eye fundus of a subject's eye with the light emitted by the illumination unit, an observation unit configured to form an eye fundus image by receiving light, which is emitted from the illumination unit and reflected from the eye fundus, and an imaging unit configured to pick up the eye fundus image formed by the observation unit.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: September 3, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Manabu Wada, Shigeaki Ono, Shinya Tanaka
  • Publication number: 20130216281
    Abstract: A transfer device includes a direct-current (DC) power supply configured to output a DC voltage; an alternating-current (AC) power supply configured to selectively output a superimposed voltage in which an AC voltage is superimposed on the DC voltage output from the DC power supply or the DC voltage output from the DC power supply; and a transfer unit configured to transfer a developer to a sheet using the voltage output from the AC power supply.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 22, 2013
    Inventors: Katsuhito Suzuki, Masahide Nakaya, Tomokazu Takeuchi, Shinya Tanaka
  • Publication number: 20130214279
    Abstract: A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 22, 2013
    Inventors: Jun Nishimura, Hideki Kitagawa, Atsuhito Murai, Hajime Imai, Shinya Tanaka, Mitsunori Imade, Tetsuo Kikuchi, Junya Shimada, Kazunori Morimoto
  • Publication number: 20130201610
    Abstract: The present invention provides a circuit board with a reduced circuit area, and a display device comprising the circuit board and a narrower picture frame. The circuit board of the present invention comprises: a bottom gate thin film transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and a top gate thin film transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor layer and the second semiconductor layer are formed from the same material, and the first drain electrode or the first source electrode and the second gate electrode are connected without interposing any other thin film transistor therebetween, and have the same electric potential.
    Type: Application
    Filed: January 25, 2011
    Publication date: August 8, 2013
    Inventors: Chikao Yamasaki, Shinya Tanaka, Tetsuo Kikuchi, Junya Shimada
  • Publication number: 20130195483
    Abstract: A transfer device includes a transfer bias power source, a switching device, and a sheet dependent condition setting device. The transfer bias power source applies to a transfer member, based on sheet dependent conditions for a recording medium onto which a toner image is transferred, one of a DC transfer bias and a superimposed transfer bias including an alternating current (AC) component superimposed on a DC component. The switching device switches a transfer mode between a DC transfer mode in which the DC transfer bias is applied to the transfer device and a superimposed-bias transfer mode in which the superimposed transfer bias is applied to the transfer device. The sheet dependent condition setting device sets arbitrarily at least one of the sheet dependent conditions for the recording medium at the superimposed-bias transfer mode. The sheet dependent conditions include a DC component value and an AC component value.
    Type: Application
    Filed: January 23, 2013
    Publication date: August 1, 2013
    Inventors: Yasunobu Shimizu, Shinya Tanaka, Hiromi Ogiyama, Hirokazu Ishii, Keigo Nakamura