Abstract: A semiconductor device that operates with reduced power consumption having a clock transfer blocking circuit and an external data transfer blocking circuit that blocks a clock signal and a data signal from being transferred to a data output circuit when a data signal captured by a data capturing circuit is to be latched by a latch circuit. If however, the data signal captured is necessary for a later stage of the semiconductor device, then an internal data transfer blocking circuit blocks the data signal from being latched in the latch circuit, while the clock transfer blocking circuit and the external data transfer blocking circuit cause the captured clock signal and data signal to be output to the data output circuit.

Abstract: A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.

Abstract: A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.

Abstract: A bias circuit generates a first voltage at a first node. A second current source generates, according to the first voltage, a power supply current to be supplied to an internal circuit including transistors. A correcting transistor in a correcting circuit supplies the first node with a correcting current generated according to a constant voltage. Because of this, the first voltage is adjusted according to the correcting current. Therefore, the operating speed of the internal circuit is prevented from changing, being dependent on the variation of the threshold voltage and temperature variation of a transistor. As a result, the yield can be improved, independently of the variation of the threshold voltage among semiconductor integrated circuit chips, which occurs in a fabrication process. Further, temperature dependency of the operating speed of the internal circuit can be reduced, which can improve the yield of the semiconductor integrated circuit.

Abstract: The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device which has a small element size and a wide opening ratio, and can reduce a kTC noise. A photodiode 10, a reset transistor 12, a source follower amplifier 14, and a horizontal selection transistor 16 are formed in each of pixel regions Pmn. A kTC noise reduction circuit 6VR1 for reducing a kTC noise and a CDS circuit 6CL1 are formed outside of the pixel regions Pmn. A differential amplifier is constituted by a first differential transistor 62 of the kTC noise reduction circuit 6VR1 and the source follower amplifier 14 in each of the pixel regions Pmn.

Abstract: An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

Abstract: The present invention provides a data driver on which an operation test can be easily and reliably conducted at the stage of manufacture and for which the testing time can be reduced and a display utilizing the same. A select switch portion 60 is provided for electrically connecting and disconnecting a ladder resistor portion 56 and selector portions 58. At the ends of wiring of grayscale voltage lines l1 through l64 opposite to the ladder resistor portion 56, there is provided a state setting circuit 62 which sets each of the grayscale lines l1 through l64 at a “High” level or a “Low” level or which sets the ends of the grayscale voltage lines l1 through l64 in a high impedance state. The state setting circuit 62 is further connected to a testing control portion 64 incorporating a shift register which operates in synchronism with a test clock TST-CLK.

Abstract: Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.

Abstract: Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.

Abstract: A transfer circuit 25 includes two sets of an input circuit 52A and an output circuit 53B, which allows bidirectional transfer. The input circuit 52A decomposes external input data signals DI11A and DI12A to signals on lines L11 to L14 in synchronism with a clock signal CLK in order to reduce the frequency thereof. The output circuit 53B composes the decomposed signals in synchronism with the clock signal CLK to regenerate the original signals and output them as external output data signals DO11B and DO12B. Signals on either the lines L11 to L14 or L21 to L24 are selected by a multiplexer 57 to provide to a main body circuit.

Abstract: In a data driver 10A of a dot-inversion driving type, the outputs of voltage buffer amplifiers B1 to B12 are connected to respective data bus lines D1 to D12 of a LCD panel, short-circuiting switches S1, S3, S5, S7, S9 and S11 are connected between ones of every other adjacent data bus lines concerned with the same display color, and interconnecting lines on first and second rows are arranged in a staggered configuration. These short-circuiting switches are formed at one sides of every other data bus lines, and turned on by a control circuit 13 when the outputs of the voltage buffer amplifier are in a high impedance state.

Abstract: A bias circuit generates a first voltage at a first node. A second current source generates, according to the first voltage, a power supply current to be supplied to an internal circuit including transistors. A correcting transistor in a correcting circuit supplies the first node with a correcting current generated according to a constant voltage. Because of this, the first voltage is adjusted according to the correcting current. Therefore, the operating speed of the internal circuit is prevented from changing, being dependent on the variation of the threshold voltage and temperature variation of a transistor. As a result, the yield can be improved, independently of the variation of the threshold voltage among semiconductor integrated circuit chips, which occurs in a fabrication process. Further, temperature dependency of the operating speed of the internal circuit can be reduced, which can improve the yield of the semiconductor integrated circuit.

Abstract: In the LCD panel driving circuit, the voltage of first and second buffer amplifiers is supplied to first output pad, the voltage of second and third buffer amplifiers is supplied to second output pad, and voltage of third and fourth buffer amplifiers is supplied to third output pad. Thus, data-line selection switches and output-polarity selection switches are switched in such a way that the voltage supplied to any adjacent output pads is always supplied from adjacent buffer amplifiers.

Abstract: A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.

Abstract: A display device includes a plurality of data drivers which are cascade-connected, and prevents variation of the duty ratio of a signal caused by accumulation of errors. In each of the plurality of data drivers: a first input circuit receives a first signal supplied from outside; a second input circuit receives a second signal supplied from outside, in response to the first signal received by the first input circuit; a signal processing circuit performs signal processing based on the second signal received by the second input circuit; a first output circuit inverts the first signal received by the first input circuit, and outputs the inverted first signal; and a second output circuit delays the second signal received by the second input circuit, by a predetermined amount, and outputs the delayed second signal.

Abstract: A selector circuit comprises four 2-input selectors 50 to 53 each selecting in response to the complementary selection signals D2 and *D2 of MSB and a 4-input selector 24A selecting in response to complementary selection signals D1, *D1, D0 and *D0 of the lower 2 bit. In each of the 2-input selectors 50 to 53, one ends of two switching transistors are commonly connected to each other and the two switching transistors are adjacently arranged in the same row. In the 4-input selector 24A, 4 analogue switch circuits, each of which has two switching transistors arranged in the same row and serially connected, are arranged in parallel to one another and each is arranged in the same row as that of a corresponding 2-input selector. Same selectors are arranged in a row on a substrate and trunk lines for providing two families of gradation potentials V0 to V7 to the circuits are laid above the circuits. Upper/lower trunk line pairs are in the third and second wiring layer, respectively.

Abstract: A selector circuit, for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, comprises: a plurality of select transistor arrays, which are provided in parallel between terminals of the gray level reference voltages and an output terminal and which have a plurality of serially connected transistors that are drive-controlled by the input data, wherein the select transistor arrays are each commonly provided for a group of M (M is a plurality and M<2N) gray level reference voltages among the 2N gray level reference voltages and are made to assume a drive enabled state by means of time division in correspondence with the M gray level reference voltages.

Abstract: An integrated circuit includes a first signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input signal, followed by outputting the first input signal after logic inversion thereof in response to a first state of a switching signal and outputting the first input signal without logic inversion in response to a second state of the switching signal, a signal processing circuit which performs signal processing based on the output of the first signal-inversion switching circuit, and a second signal-inversion switching circuit which receives the output of the first signal-inversion switching circuit passing through the signal processing circuit as a second input signal, followed by outputting the second input signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input signal without logic inversion in response to the first state of the switching signal.

Abstract: An operational amplifier, which generates an output voltage at an output terminal that is equal to an input voltage, comprises: a differential circuit, which compares the input voltage and the output voltage; first and second output transistors, which are controlled by the output of the differential circuit to drive the output terminal; and an offset cancel circuit, connected with the differential circuit, for storing an offset amount of this differential circuit, wherein, in the offset cancel period in which the offset amount is stored by the offset cancel circuit, the output terminal is driven by the second output transistor, and in the operational amplifier operation period following the offset cancel period, the output terminal is driven by the first output transistor.

Abstract: A transfer circuit 25 includes two sets of an input circuit 52A and an output circuit 53B, which allows bidirectional transfer. The input circuit 52A decomposes external input data signals DI11A and DI12A to signals on lines L11 to L14 in synchronism with a clock signal CLK in order to reduce the frequency thereof. The output circuit 53B composes the decomposed signals in synchronism with the clock signal CLK to regenerate the original signals and output them as external output data signals DO11B and DO12B. Signals on either the lines L11 to L14 or L21 to L24 are selected by a multiplexer 57 to provide to a main body circuit.