Patents by Inventor Shinya Yamakawa

Shinya Yamakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10686397
    Abstract: A motor system according to the present invention includes: a motor including a first winding portion and a second winding portion, the second winding portion having a larger number of turns than the first winding portion; a first inverter connected to the first winding portion; and a second inverter connected to the second winding portion.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 16, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeo Umehara, Koichi Arisawa, Yosuke Shinomoto, Takashi Yamakawa, Shinya Toyodome
  • Publication number: 20200144262
    Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.
    Type: Application
    Filed: December 26, 2019
    Publication date: May 7, 2020
    Inventors: Shinya Yamakawa, Yasushi Tateshita
  • Publication number: 20200127554
    Abstract: A power converting apparatus includes: a boost circuit including a reactor supplied with first voltage output from an alternating-current power supply, a first leg including first upper-arm and lower-arm switching elements connected in series, and a second leg connected in parallel with the first leg and including second upper-arm and lower-arm switching elements connected in series, and boosting the first voltage; a first voltage detecting unit detecting the first voltage; a smoothing capacitor smoothing voltage output from the boost circuit; and a second voltage detecting unit detecting second voltage smoothed by the smoothing capacitor. When the second voltage is larger than the first voltage and is lower than or equal to twice the first voltage, a width of a second drive pulse to turn on the first upper-arm switching element is larger than a width of a first drive pulse to turn on the first lower-arm switching element.
    Type: Application
    Filed: June 26, 2017
    Publication date: April 23, 2020
    Inventors: Shinya TOYODOME, Takashi YAMAKAWA, Shigeo UMEHARA
  • Patent number: 10559567
    Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 11, 2020
    Assignee: Sony Corporation
    Inventors: Shinya Yamakawa, Yasushi Tateshita
  • Publication number: 20200021232
    Abstract: An over-current protection circuit for a motor capable of selecting one of a plurality of connection states has a plurality of decision circuits, a combining circuit, and a nullifying circuit. The combining circuit combines results of the comparisons in the plurality of decision circuits. The nullifying circuit nullifies part of the comparisons in the plurality of decision circuits. The number of outputs of the over-current protection circuit is one, so that for controlling the driving and stopping of the inverter needs just one terminal is required for receiving the output of the combining circuit. Moreover, because the over-current protection circuit is formed of hardware, the protection can be performed at a high speed.
    Type: Application
    Filed: October 31, 2016
    Publication date: January 16, 2020
    Inventors: Kenji IWAZAKI, Koichi ARISAWA, Takashi YAMAKAWA, Keisuke UEMURA, Shinya TOYODOME
  • Publication number: 20200021231
    Abstract: An air conditioner includes a compressor to compress a refrigerant used in a refrigeration cycle, a converter to generate a DC voltage, an inverter to generate three-phase AC voltages from the DC voltage, a motor to produce a driving force for driving the compressor with a plurality of coils, the three-phase AC voltages being applied to the coils, a connection switching unit to switch connection states of the coils between a first connection state and a second connection state, and a controller to detect an abnormality of the connection switching unit.
    Type: Application
    Filed: October 31, 2016
    Publication date: January 16, 2020
    Inventors: Takashi YAMAKAWA, Koichi ARISAWA, Kenji IWAZAKI, Keisuke UEMURA, Shinya TOYODOME
  • Patent number: 10483306
    Abstract: A photoelectric conversion element according to one embodiment of the disclosure includes a photoelectric conversion region inside a semiconductor layer. The photoelectric conversion region includes a region in which a depletion region is to be formed by voltage application to the semiconductor layer. The semiconductor layer has a first main surface and a second main surface. The depletion region converts light into a photoelectron, in which the light enters from side on which the first main surface is disposed. The photoelectric conversion element further includes an isoelectronic trap region in the region in which the depletion region is to be formed.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: November 19, 2019
    Assignee: Sony Corporation
    Inventors: Shinya Yamakawa, Jun Komachi, Koji Nagahiro
  • Publication number: 20190245472
    Abstract: In a motor driving apparatus having an inverter for driving a motor capable of switching between a star connection and a delta connection, when currents detected by winding current detecting elements detecting currents flowing through windings become excessive, the inverter is made to stop. Moreover, inverter output currents are calculated after removing a circulating current component at the time of the delta connection, from the winding currents detected by the winding current detecting elements, and the inverter is controlled using the calculated inverter output currents. Because over-current protection is performed based on the detected values of the winding currents, it is possible to prevent demagnetization taking account oSf the circulating current. Also, the inverter control is prevented from being affected by the circulating current in the delta connection. Accordingly, it is possible to reduce the number of the current detecting elements, and perform the over-current protection and control properly.
    Type: Application
    Filed: October 31, 2016
    Publication date: August 8, 2019
    Inventors: Shinya TOYODOME, Takashi YAMAKAWA, Koichi ARISAWA, Keisuke UEMURA, Kenji IWAZAKI
  • Patent number: 10340298
    Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus capable of reducing a leak current of a PN junction region. In a Si substrate, an N+ region is formed in a P-type Well (P_Well region). A depletion layer is formed in the circumference of a boundary (metallurgic boundary of a PN junction) between the P_Well region and the N+ region. On the surface of the Si substrate, a fixed charge layer having positive fixed charge is formed on the N+ region to be spanned to the depletion layer. The present disclosure is applicable to a CMOS solid-state imaging device used in an imaging apparatus such as a camera.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: July 2, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shinya Yamakawa, Satoe Miyata
  • Publication number: 20190157271
    Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 23, 2019
    Inventors: Shinya Yamakawa, Yasushi Tateshita
  • Publication number: 20190140575
    Abstract: A motor system according to the present invention includes: a motor including a first winding portion and a second winding portion, the second winding portion having a larger number of turns than the first winding portion; a first inverter connected to the first winding portion; and a second inverter connected to the second winding portion.
    Type: Application
    Filed: June 17, 2016
    Publication date: May 9, 2019
    Inventors: Shigeo UMEHARA, Koichi ARISAWA, Yosuke SHINOMOTO, Takashi YAMAKAWA, Shinya TOYODOME
  • Patent number: 10269801
    Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Sony Corporation
    Inventors: Shinya Yamakawa, Yasushi Tateshita
  • Publication number: 20190103501
    Abstract: A light-receiving device of an embodiment of the present disclosure includes, on a first principal surface of a semiconductor layer, a pixel region that includes a plurality of light-receiving pixels each receiving light incident from side of a second principal surface of the semiconductor layer. The light-receiving device further includes, throughout a gap between the second principal surface and the pixel region, a low-impurity region having a relatively lower impurity concentration than the pixel region. The light-receiving pixels each include one or a plurality of photoelectric current extraction regions each including, on the first principal surface, an anode region and a cathode region, and a circuit region that is electrically coupled to each of the cathode regions and is electrically separated from the impurity region.
    Type: Application
    Filed: February 15, 2017
    Publication date: April 4, 2019
    Applicant: SONY CORPORATION
    Inventors: Takahiro IGARASHI, Takahiro SONODA, Atsushi SUZUKI, Shinya YAMAKAWA, Hiroshi YUMOTO, Izuho HATADA, Takeshi KODAMA, Kiwamu ADACHI, Katsuji MATSUMOTO
  • Publication number: 20190074312
    Abstract: A photoelectric conversion element according to one embodiment of the disclosure includes a photoelectric conversion region inside a semiconductor layer. The photoelectric conversion region includes a region in which a depletion region is to be formed by voltage application to the semiconductor layer. The semiconductor layer has a first main surface and a second main surface. The depletion region converts light into a photoelectron, in which the light enters from side on which the first main surface is disposed. The photoelectric conversion element further includes an isoelectronic trap region in the region in which the depletion region is to be formed.
    Type: Application
    Filed: February 6, 2017
    Publication date: March 7, 2019
    Applicant: SONY CORPORATION
    Inventors: Shinya YAMAKAWA, Jun KOMACHI, Koji NAGAHIRO
  • Patent number: 10224362
    Abstract: A solid-state image pickup element including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: March 5, 2019
    Assignee: SONY CORPORATION
    Inventor: Shinya Yamakawa
  • Publication number: 20180138179
    Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 17, 2018
    Inventors: Shinya Yamakawa, Yasushi Tateshita
  • Patent number: 9881920
    Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: January 30, 2018
    Assignee: Sony Corporation
    Inventors: Shinya Yamakawa, Yasushi Tateshita
  • Publication number: 20170304581
    Abstract: A state control apparatus including: an acquiring unit configured to acquire a state index indicating a state of target feeling based on biological information corresponding to the target feeling which is feeling of a target to be guided, the biological information being detected from a guide target whose state of feeling is to be guided; and a state control unit configured to determine a feeling guiding medium to be used for guiding the state of the target feeling based on the acquired state index and pattern information which is associated with the feeling guiding medium for guiding the state of the target feeling and which indicates a pattern of temporal change of the state index so that the state of the target feeling becomes a predetermined set state, and control the state of the target feeling of the guide target by performing processing relating to the determined feeling guiding medium. The biological information includes information indicating a detection result of an enzyme.
    Type: Application
    Filed: July 16, 2015
    Publication date: October 26, 2017
    Applicant: Sony Corporation
    Inventors: Nobuyuki Kuboi, Takashi Kinoshita, Shinya Yamakawa
  • Publication number: 20170294475
    Abstract: A solid-state image pickup element including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventor: Shinya Yamakawa
  • Patent number: 9728576
    Abstract: A solid-state image pickup element including: a photoelectric conversion region; a transistor; an isolation region of a first conductivity type configured to isolate the photoelectric conversion region and the transistor from each other; a well region of the first conductivity type having the photoelectric conversion region, the transistor, and the isolation region of the first conductivity type formed therein; a contact portion configured to supply an electric potential used to fix the well region to a given electric potential; and an impurity region of the first conductivity type formed so as to extend in a depth direction from a surface of the isolation region of the first conductivity type in the isolation region of the first conductivity type between the contact portion and the photoelectric conversion region, and having a sufficiently higher impurity concentration than that of the isolation region of the first conductivity type.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 8, 2017
    Assignee: SONY CORPORATION
    Inventor: Shinya Yamakawa