Patents by Inventor Shinya Yamakawa
Shinya Yamakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145522Abstract: Provided are a solid-state imaging device, a manufacturing method thereof, and an electronic device that enable improvement of the sensitivity in a near infrared region by a simpler process. A solid-state imaging device includes a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed, a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed, and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other.Type: ApplicationFiled: November 2, 2023Publication date: May 2, 2024Inventor: SHINYA YAMAKAWA
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Patent number: 11940754Abstract: A container member includes a container body that contains a recording medium and that tilts with respect to a horizontal direction such that a leading edge of the contained recording medium is higher than a trailing edge, a trailing edge restriction portion that comes into contact with the trailing edge of the recording medium that is contained in the container body in a front-rear direction of the recording medium and that restricts a position of the trailing edge of the recording medium, and a restriction portion that restricts movement of the trailing edge in a thickness direction of the recording medium that is contained in the container body.Type: GrantFiled: December 20, 2021Date of Patent: March 26, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Shinya Hasegawa, Kota Tomioka, Hiroyuki Tanaka, Yoichi Yamakawa
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Patent number: 11942493Abstract: An imaging device in which noise can be reduced, and an electronic device using this device. The imaging device includes a light receiving element, and a read circuit. A field effect transistor in the read circuit has a semiconductor layer in which a channel is formed, a gate electrode that covers the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode. The semiconductor layer has a main surface, and a first side surface on one end side of the main surface in a gate width direction of the field effect transistor. The gate electrode has a first portion that faces the main surface via the gate insulating film, and a second portion that faces the first side surface via the gate insulating film. A crystal plane of the first side surface is a plane or a plane equivalent to the plane.Type: GrantFiled: September 17, 2020Date of Patent: March 26, 2024Assignee: Sony Semiconductor Solutions CorporationInventor: Shinya Yamakawa
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Patent number: 11926501Abstract: An accommodating device includes a device body, an accommodating unit that is movable to a supply position where a user is able to supply a medium by being pulled out from the device body in a pulling direction and of which a centroid position is located on one side surface side with respect to a center in an intersecting direction with the pulling direction, a first expanding and contracting member that expands and contracts to connect the accommodating unit to the device body so as to be able to be pulled out and is fixed to one side surface of the accommodating unit in the intersecting direction, and a second expanding and contracting member that expands and contracts to connect the accommodating unit to the device body so as to be able to be pulled out and is fixed at a position higher than the first expanding and contracting member on the other side surface of the accommodating unit in the intersecting direction.Type: GrantFiled: May 5, 2022Date of Patent: March 12, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Kota Tomioka, Hiroyuki Tanaka, Yoichi Yamakawa, Shinya Hasegawa
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Patent number: 11830906Abstract: Provided are a solid-state imaging device, a manufacturing method thereof, and an electronic device. The solid-state imaging device includes a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed, a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed, and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other.Type: GrantFiled: June 23, 2022Date of Patent: November 28, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Shinya Yamakawa
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Publication number: 20230246032Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.Type: ApplicationFiled: April 6, 2023Publication date: August 3, 2023Inventors: Shinya Yamakawa, Yasushi Tateshita
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Patent number: 11664376Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.Type: GrantFiled: April 30, 2021Date of Patent: May 30, 2023Assignee: Sony Group CorporationInventors: Shinya Yamakawa, Yasushi Tateshita
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Publication number: 20220399396Abstract: Provided are a solid-state imaging device, a manufacturing method thereof, and an electronic device that enable improvement of the sensitivity in a near infrared region by a simpler process. A solid-state imaging device includes a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed, a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed, and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other.Type: ApplicationFiled: June 23, 2022Publication date: December 15, 2022Inventor: SHINYA YAMAKAWA
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Publication number: 20220384501Abstract: There is provided a solid state image sensor including a photoelectric conversion unit formed and embedded in a semiconductor substrate, an impurity region that retains an electric charge generated by the photoelectric conversion unit, and a transfer transistor that transfers the electric charge to the impurity region. A gate electrode of the transfer transistor is formed in a depth direction toward the photoelectric conversion unit in the semiconductor substrate, from a surface of the semiconductor substrate on which the impurity region is formed. A channel portion of the transfer transistor is surrounded by the gate electrode in two or more directions other than a direction of the impurity region, as seen from the depth direction.Type: ApplicationFiled: April 12, 2022Publication date: December 1, 2022Inventor: SHINYA YAMAKAWA
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Publication number: 20220302192Abstract: An imaging device in which noise can be reduced, and an electronic device using this device. The imaging device includes a light receiving element, and a read circuit. A field effect transistor in the read circuit has a semiconductor layer in which a channel is formed, a gate electrode that covers the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode. The semiconductor layer has a main surface, and a first side surface on one end side of the main surface in a gate width direction of the field effect transistor. The gate electrode has a first portion that faces the main surface via the gate insulating film, and a second portion that faces the first side surface via the gate insulating film. A crystal plane of the first side surface is a plane or a plane equivalent to the plane.Type: ApplicationFiled: September 17, 2020Publication date: September 22, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Shinya YAMAKAWA
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Patent number: 11398522Abstract: The present technology relates to a solid-state imaging device, a manufacturing method thereof, and an electronic device that enable improvement of the sensitivity in a near infrared region by a simpler process. A solid-state imaging device includes: a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed; a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed; and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other. The present technology can be applied to a CMOS image sensor.Type: GrantFiled: November 1, 2017Date of Patent: July 26, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Shinya Yamakawa
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Patent number: 11322533Abstract: There is provided a solid state image sensor including a photoelectric conversion unit formed and embedded in a semiconductor substrate, an impurity region that retains an electric charge generated by the photoelectric conversion unit, and a transfer transistor that transfers the electric charge to the impurity region. A gate electrode of the transfer transistor is formed in a depth direction toward the photoelectric conversion unit in the semiconductor substrate, from a surface of the semiconductor substrate on which the impurity region is formed. A channel portion of the transfer transistor is surrounded by the gate electrode in two or more directions other than a direction of the impurity region, as seen from the depth direction.Type: GrantFiled: February 28, 2014Date of Patent: May 3, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Shinya Yamakawa
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Publication number: 20210384237Abstract: A solid-state imaging element including: a first substrate including a photoelectric conversion section and a transfer transistor electrically coupled to the photoelectric conversion section; a second substrate provided to be opposed to the first substrate and including an output transistor, the output transistor including a gate electrode, a channel region of a first electrical conductivity type disposed to be opposed to the gate electrode, and source-drain regions of the first electrical conductivity type adjacent to the channel region; and a drive circuit that allows a signal electric charge generated in the photoelectric conversion section to be outputted through the transfer transistor and the output transistor.Type: ApplicationFiled: October 10, 2019Publication date: December 9, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Shinya YAMAKAWA
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Publication number: 20210335880Abstract: The present technology relates to a solid-state imaging device, a manufacturing method thereof, and an electronic device that enable improvement of the sensitivity in a near infrared region by a simpler process. A solid-state imaging device includes: a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed; a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed; and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other. The present technology can be applied to a CMOS image sensor.Type: ApplicationFiled: November 1, 2017Publication date: October 28, 2021Inventor: SHINYA YAMAKAWA
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Publication number: 20210265347Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.Type: ApplicationFiled: April 30, 2021Publication date: August 26, 2021Inventors: Shinya Yamakawa, Yasushi Tateshita
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Patent number: 11011518Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.Type: GrantFiled: December 26, 2019Date of Patent: May 18, 2021Assignee: Sony CorporationInventors: Shinya Yamakawa, Yasushi Tateshita
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Patent number: 10821260Abstract: A state control apparatus including: an acquiring unit configured to acquire a state index indicating a state of target feeling based on biological information corresponding to the target feeling which is feeling of a target to be guided, the biological information being detected from a guide target whose state of feeling is to be guided; and a state control unit configured to determine a feeling guiding medium to be used for guiding the state of the target feeling based on the acquired state index and pattern information which is associated with the feeling guiding medium for guiding the state of the target feeling and which indicates a pattern of temporal change of the state index so that the state of the target feeling becomes a predetermined set state, and control the state of the target feeling of the guide target by performing processing relating to the determined feeling guiding medium. The biological information includes information indicating a detection result of an enzyme.Type: GrantFiled: July 16, 2015Date of Patent: November 3, 2020Assignee: Sony CorporationInventors: Nobuyuki Kuboi, Takashi Kinoshita, Shinya Yamakawa
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Publication number: 20200144262Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.Type: ApplicationFiled: December 26, 2019Publication date: May 7, 2020Inventors: Shinya Yamakawa, Yasushi Tateshita
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Patent number: 10559567Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.Type: GrantFiled: January 7, 2019Date of Patent: February 11, 2020Assignee: Sony CorporationInventors: Shinya Yamakawa, Yasushi Tateshita
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Patent number: 10483306Abstract: A photoelectric conversion element according to one embodiment of the disclosure includes a photoelectric conversion region inside a semiconductor layer. The photoelectric conversion region includes a region in which a depletion region is to be formed by voltage application to the semiconductor layer. The semiconductor layer has a first main surface and a second main surface. The depletion region converts light into a photoelectron, in which the light enters from side on which the first main surface is disposed. The photoelectric conversion element further includes an isoelectronic trap region in the region in which the depletion region is to be formed.Type: GrantFiled: February 6, 2017Date of Patent: November 19, 2019Assignee: Sony CorporationInventors: Shinya Yamakawa, Jun Komachi, Koji Nagahiro