Abstract: Systems and methods for scheduling instructions without instruction decode. In one embodiment, a multi-core processor includes a scheduling unit in each core for scheduling instructions from two or more threads scheduled for execution on that particular core. As threads are scheduled for execution on the core, instructions from the threads are fetched into a buffer without being decoded. The scheduling unit includes a macro-scheduler unit for performing a priority sort of the two or more threads and a micro-scheduler arbiter for determining the highest order thread that is ready to execute. The macro-scheduler unit and the micro-scheduler arbiter use pre-decode data to implement the scheduling algorithm. The pre-decode data may be generated by decoding only a small portion of the instruction or received along with the instruction. Once the micro-scheduler arbiter has selected an instruction to dispatch to the execution unit, a decode unit fully decodes the instruction.

Abstract: One embodiment of the present invention sets forth a technique instruction level and compute thread array granularity execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. When preemption is performed at a compute thread array boundary, the amount of context state to be stored is reduced because execution units within the processing pipeline complete execution of in-flight instructions and become idle. If, the amount of time needed to complete execution of the in-flight instructions exceeds a threshold, then the preemption may dynamically change to be performed at the instruction level instead of at compute thread array granularity.

Abstract: One embodiment of the present invention sets forth a technique instruction level and compute thread array granularity execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. When preemption is performed at a compute thread array boundary, the amount of context state to be stored is reduced because execution units within the processing pipeline complete execution of in-flight instructions and become idle. If, the amount of time needed to complete execution of the in-flight instructions exceeds a threshold, then the preemption may dynamically change to be performed at the instruction level instead of at compute thread array granularity.

Abstract: A method for context switching on a video processor having a scalar execution unit and a vector execution unit. The method includes executing a first task and a second task on a vector execution unit. The first task in the second task can be from different respective contexts. The first task and the second task are each allocated to the vector execution unit from a scalar execution unit. The first task and the second task each comprise a plurality of work packages. In response to a switch notification, a work package boundary of the first task is designated. A context switch from the first task to the second task is then executed on the work package boundary.

Abstract: A stream based memory access system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A frame buffer memory is included for storing data for the scalar execution unit and the vector execution unit. A memory interface is included for establishing communication between the scalar execution unit and the vector execution unit and the frame buffer memory. The frame buffer memory comprises a plurality of tiles. The memory interface implements a first sequential access of tiles and implements a second stream comprising a second sequential access of tiles for the vector execution unit or the scalar execution unit.

Abstract: One embodiment sets forth a technique for N-way memory barrier operation coalescing. When a first memory barrier is received for a first thread group execution of subsequent memory operations for the first thread group are suspended until the first memory barrier is executed. Subsequent memory barriers for different thread groups may be coalesced with the first memory barrier to produce a coalesced memory barrier that represents memory barrier operations for multiple thread groups. When the coalesced memory barrier is being processed, execution of subsequent memory operations for the different thread groups is also suspended. However, memory operations for other thread groups that are not affected by the coalesced memory barrier may be executed.

Abstract: An apparatus and method of detecting scene changes within a video frame sequence. A video data frame pixel array is partitioned into pixel groups within a frame difference engine. Video data matching of each pixel group is compared between a preceding and following video frame. By way of example pixel group matching can be determined in response to comparing the sums of absolute pixel luminance and/or chrominance differences between corresponding pixels in corresponding pixel groups within the sequential frames against a threshold value. If an insufficient number of pixel groups match, then a scene change signal is output, such as to the encoder which decides whether to encode the entire frame or changes from prior frames. A media communication system is also described, preferably implemented within an SoC, which wirelessly communicates encoded video data for substantially simultaneous viewing by a receiver.

Abstract: A dynamic allocation of available ASV buffer memory space is performed on each pack in a DVD-A bitstream one pack at a time. Concurrently, an ASV buffer table is updated for each type of data pack currently being processed. The ASV buffer table includes pointers corresponding to the various fields that form a particular ASV frame. In this way, only that memory that is required to store a particular ASV frame is used thereby allowing the ASV buffer memory to be configured on the fly in such a manner as to efficiently store the required ASV frame data. When a particular ASV frame is to be displayed, or otherwise processed, the ASV buffer table is accessed, and the particular pointers for a specific ASV frame are looked up and used to access the desired ASV frame.

Abstract: An apparatus and method for providing enhanced performance for multi-processor multimedia chips. In one embodiment, the present invention is comprised of a data and communication apparatus coupled with the multimedia system in which the multi-processor multimedia chips are disposed. The present invention is comprised of a data memory to retrievably store data. The present invention is further comprised of an instruction memory to retrievably store instructions. The present invention is also comprised of an incoming buffer which permits transfer of data into the data and communication apparatus and provides fast access to streaming data. The present invention is additionally comprised of an outgoing buffer which monitors and permits transfer of data out of the data and communication apparatus.

Abstract: When switching between a DVD-video mode and a DVD-audio mode in a DVD-A/V player, a current video frame is stored in a current display buffer portion of the memory during the DVD-video mode. The DVD-A/V player is paused in the DVD-video mode and set in the DVD-audio mode. If it is determined that the current display buffer portion of the memory is a reserved display buffer portion of the memory, then the current video frame is copied to a reconstructed display buffer portion of the memory. At least the current display portion of the memory is designated as an ASV buffer and a frame buffer management scheme is changed so as to preserve the ASV buffer.

Abstract: A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

Abstract: A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.

Abstract: A stream based memory access system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A frame buffer memory is included for storing data for the scalar execution unit and the vector execution unit. A memory interface is included for establishing communication between the scalar execution unit and the vector execution unit and the frame buffer memory. The frame buffer memory comprises a plurality of tiles. The memory interface implements a first sequential access of tiles and implements a second stream comprising a second sequential access of tiles for the vector execution unit or the scalar execution unit.

Abstract: A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.

Abstract: A system and method for rendering multiple windows across multiple display planes utilizing a sliced rendering data pathway architecture for achieving a highly area efficient design of the graphics display system. Windows across multiple display planes are rendered from direct memory access fetch engines retrieving pixel data from memory. Rendering data pathways are shared between direct memory access fetch engines directed to a single display plane. Furthermore, the rendering data pathways can be time sliced wherein data from multiple planes are time multiplexed through the rendering pathway. The invention allows creating a graphical engine with a lower gate count than conventional circuits. The resultant system is modular and scalable, while being customizable from lower power applications to HDTV sets.

Abstract: Embodiments of the present invention provide a memory controller comprising a front-end module, a back-end module communicatively coupled to the front-end module, and a physical interface module communicatively coupled to the back-end module. The front-end module generates a plurality of page packets from a plurality of received memory commands, wherein the order of receipt of said memory commands is preserved. The back-end module dynamically issues a next one of the plurality of page packets while issuing a current one of the plurality of page packets. The physical interface module causes a plurality of transfers according to the dynamically issued current one and next one of the plurality of page packets.

Abstract: An apparatus and method of detecting scene changes within a video frame sequence. A video data frame pixel array is partitioned into pixel groups within a frame difference engine. Video data matching of each pixel group is compared between a preceding and following video frame. By way of example pixel group matching can be determined in response to comparing the sums of absolute pixel luminance and/or chrominance differences between corresponding pixels in corresponding pixel groups within the sequential frames against a threshold value. If an insufficient number of pixel groups match, then a scene change signal is output, such as to the encoder which decides whether to encode the entire frame or changes from prior frames. A media communication system is also described, preferably implemented within an SoC, which wirelessly communicates encoded video data for substantially simultaneous viewing by a receiver.

Abstract: Embodiments of the present invention provide a memory controller comprising a front-end module, a back-end module communicatively coupled to the front-end module, and a physical interface module communicatively coupled to the back-end module. The front-end module generates a plurality of page packets from a plurality of received memory commands, wherein the order of receipt of said memory commands is preserved. The back-end module dynamically issues a next one of the plurality of page packets while issuing a current one of the plurality of page packets. The physical interface module causes a plurality of transfers according to the dynamically issued current one and next one of the plurality of page packets.

Abstract: A system and method for flexibly blending multiple image planes in a video device comprises a timing controller configured to generate adjusted synchronization signals for pretiming multiple video image planes. The timing controller preferably generates the adjusted synchronization signals in response to programmable delay signals and a master synchronization signal. A blender device then receives and flexibly combines the multiple video image planes to generate a synchronized composite blender output signal. The blender preferably includes a selectable pseudo-output signal that may be routed through an external processing device, and returned as a feedback loop to an external input of the blender device.

Abstract: A dynamic allocation of available ASV buffer memory space is performed on each pack in a DVD-A bitstream one pack at a time. Concurrently, an ASV buffer table is updated for each type of data pack currently being processed. The ASV buffer table includes pointers corresponding to the various fields that form a particular ASV frame. In this way, only that memory that is required to store a particular ASV frame is used thereby allowing the ASV buffer memory to be configured on the fly in such a manner as to efficiently store the required ASV frame data. When a particular ASV frame is to be displayed, or otherwise processed, the ASV buffer table is accessed, and the particular pointers for a specific ASV frame are looked up and used to access the desired ASV frame.