Patents by Inventor Shirish Gadre

Shirish Gadre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030152371
    Abstract: When switching between a DVD-video mode and a DVD-audio mode in a DVD-A/V player, a current video frame is stored in a current display buffer portion of the memory during the DVD-video mode. The DVD-A/V player is paused in the DVD-video mode and set in the DVD-audio mode. If it is determined that the current display buffer portion of the memory is a reserved display buffer portion of the memory, then the current video frame is copied to a reconstructed display buffer portion of the memory. At least the current display portion of the memory is designated as an ASV buffer and a frame buffer management scheme is changed so as to preserve the ASV buffer.
    Type: Application
    Filed: February 11, 2002
    Publication date: August 14, 2003
    Applicant: Sony Corporation
    Inventors: Shirish Gadre, Fang-Chuan Wu, Elif Albuz, Raman Subramanian
  • Patent number: 6518985
    Abstract: Display hardware which manages a plurality, e.g. three, potentially overlapping display windows each having its own pixel values and potentially having its own palette, with no limitation as to the position of the windows relative to each other. This capability is provided at a reduced hardware complexity as compared to a parallel hardware approach, by arranging substantial portions of the hardware in a multiplexed fashion so that the same hardware handles the lookup of palette entries for pixel values, regardless of the currently active window. The hardware is arranged so that it may switch in real time from processing data for one window to processing data for another window, whenever the current display coordinate crosses a window boundary.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: February 11, 2003
    Assignees: Sony Corporation, Sony Electronics
    Inventors: Taner Ozcelik, Shirish Gadre, Tomonari Tohara, Prakash Bare
  • Publication number: 20020184450
    Abstract: An apparatus and method for providing enhanced performance for multi-processor multimedia chips. In one embodiment, the present invention is comprised of a data and communication apparatus coupled with the multimedia system in which the multi-processor multimedia chips are disposed. The present invention is comprised of a data memory to retrievably store data. The present invention is further comprised of an instruction memory to retrievably store instructions. The present invention is also comprised of an incoming buffer which permits transfer of data into the data and communication apparatus and provides fast access to streaming data. The present invention is additionally comprised of an outgoing buffer which monitors and permits transfer of data out of the data and communication apparatus.
    Type: Application
    Filed: May 23, 2001
    Publication date: December 5, 2002
    Inventors: Shirish Gadre, Elif Albuz
  • Publication number: 20020149626
    Abstract: Display hardware which manages a plurality, e.g. three, potentially overlapping display windows each having its own pixel values and potentially having its own palette, with no limitation as to the position of the windows relative to each other. This capability is provided at a reduced hardware complexity as compared to a parallel hardware approach, by arranging substantial portions of the hardware in a multiplexed fashion so that, for example, the same hardware handles the lookup of palette entries for pixel values, regardless of the currently active window. The hardware is arranged so that it may switch in real time from processing data for one window to processing data for another window, whenever the current display coordinate crosses a window boundary.
    Type: Application
    Filed: March 31, 1999
    Publication date: October 17, 2002
    Inventors: TANER OZCELIK, SHIRISH GADRE, TOMONARI TOHARA, PRAKASH BARE
  • Patent number: 6308253
    Abstract: A reduced programmable controller for an extensible digital signal processing architecture supports particular instructions to facilitate common digital signal processing operations. These instructions include extract and insert instructions, which are useful in managing the storage and extraction of digital signal processing variables to and from registers, and also useful in assembling fixed-length digital signal parameters from a section of a bitstream stored in a register. These instructions further include leading value detect instructions, including a leading zero detect instruction and a leading one detect instruction which are useful in parsing unique prefix codes such as Huffman codes used in MPEG encoding of video and other variable length codes, and useful in handling of a priority encoder such as a task manager.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: October 23, 2001
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Shirish Gadre, Mazin S. Khurshid
  • Patent number: 6128340
    Abstract: A decoder system is provided for decoding an input video signal. A buffer memory hold slices of reconstructed B-pictures for display. The decoder is controlled in accordance with an amount of available memory in the buffer (the amount of available memory in the buffer depends both on how much data has been decoded and also upon how much data has been displayed). In addition, a buffer memory input controller controls into which locations of the buffer memory the slices of the reconstructed B-pictures are stored. As a result, only 2.53 frames of buffer memory are required.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: October 3, 2000
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Taner Ozcelik, Shirish Gadre
  • Patent number: 6041400
    Abstract: A circuit arrangement and method utilize a distributed extensible processing architecture to allocate various DSP functions or operations between multiple processing cores disposed on an integrated circuit device. Each processing core includes one or more hardwired datapaths to provide one or more DSP operations. Moreover, each processing core includes a programmable controller that controls the operation of each hardwired datapath via a local computer program executed by the controller. Furthermore, the processing cores are coupled to one another over a communications bus to permit data to be passed between the cores and thereby permit multiple DSP operations to be performed on data supplied to the device.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: March 21, 2000
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Taner Ozcelik, Shirish Gadre, Yew-Koon Tan