Patents by Inventor Shiro Uriu

Shiro Uriu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7822888
    Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: October 26, 2010
    Assignee: Fujitsu Limited
    Inventors: Miyoshi Saito, Hisanori Fujisawa, Ichiro Kasama, Tetsuo Kawano, Kazuaki Imafuku, Hiroshi Furukawa, Shiro Uriu, Mitsuharu Wakayoshi
  • Patent number: 7774580
    Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: August 10, 2010
    Assignee: Fujitsu Limited
    Inventors: Miyoshi Saito, Hisanori Fujisawa, Hideki Yoshizawa, Tetsu Tanizawa, Ichiro Kasama, Tetsuo Kawano, Kazuaki Imafuku, Hiroshi Furukawa, Shiro Uriu, Mitsuharu Wakayoshi
  • Patent number: 7551612
    Abstract: A switch station including an ATM switch; a memory storing control data for operations of the switch station; an intra-station device, accommodating a subscriber line, performing communication operation on subscriber ATM cell; a control processor generating control information in link access protocol (LAP) format; and an interface unit converting LAP control information into ATM cell to the intra-station device through the ATM switch, wherein the control information is communicated according to LAP, the intra-station device receives the control information and transmits a direct memory access request to obtain control data stored in the memory, the interface unit obtains and converts the data format of the control data into ATM cell to transmit to the intra-station device through the switch, and the intra-station device performs the communication operation on the subscriber ATM cell based on the control data received through the switch.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: June 23, 2009
    Assignee: Fujitsu Limited
    Inventors: Yasusi Kobayashi, Yoshihiro Watanabe, Hiroshi Nishida, Masami Murayama, Naoyuki Izawa, Yasuhiro Aso, Yoshihiro Uchida, Hiromi Yamanaka, Jin Abe, Yoshihisa Tsuruta, Yoshiharu Kato, Satoshi Kakuma, Shiro Uriu, Noriko Samejima, Eiji Ishioka, Shigeru Sekine, Yoshiyuki Karakawa, Atsushi Kagawa, Mikio Nakayama, Miyuki Kawataka, Satoshi Esaka, Nobuyuki Tsutsui, Fumio Hirase, Atsuko Suzuki, Shouji Kohira, Kenichi Okabe, Takashi Hatano, Yasuhiro Nishikawa, Jun Itoh, Shinichi Araya
  • Patent number: 7453800
    Abstract: A communications apparatus for switching among different interfaces includes a switch unit. The switch unit includes a main switch for switching data of a fixed length and an interface having a first buffer for an input of the main switch and a second buffer for an output of the main switch.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: November 18, 2008
    Assignee: Fujitsu Limited
    Inventors: Ryo Takajitsuko, Kenichi Okabe, Shiro Uriu, Hiroya Kawasaki
  • Publication number: 20070150707
    Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.
    Type: Application
    Filed: March 2, 2007
    Publication date: June 28, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Shiro URIU, Mitsuharu Wakayoshi, Tetsuo Kawano, Hiroshi Furukawa, Ichiro Kasama, Kazuaki Imafuku, Toshiaki Suzuki
  • Patent number: 7227861
    Abstract: Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: June 5, 2007
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Tomonaga, Masakatsu Nagata, Kenichi Kawarai, Naoki Matsuoka, Kenichi Okabe, Shiro Uriu
  • Patent number: 7194610
    Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: March 20, 2007
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Mitsuharu Wakayoshi, Tetsuo Kawano, Hiroshi Furukawa, Ichiro Kasama, Kazuaki Imafuku, Toshiaki Suzuki
  • Publication number: 20060010306
    Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.
    Type: Application
    Filed: March 11, 2005
    Publication date: January 12, 2006
    Inventors: Miyoshi Saito, Hisanori Fujisawa, Hideki Yoshizawa, Tetsu Tanizawa, Ichiro Kasama, Tetsuo Kawano, Kazuaki Imafuku, Hiroshi Furukawa, Shiro Uriu, Mitsuharu Wakayoshi
  • Publication number: 20060004940
    Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.
    Type: Application
    Filed: October 26, 2004
    Publication date: January 5, 2006
    Inventors: Miyoshi Saito, Hisanori Fujisawa, Ichiro Kasama, Tetsuo Kawano, Kazuaki Imafuku, Hiroshi Furukawa, Shiro Uriu, Mitsuharu Wakayoshi
  • Publication number: 20060004994
    Abstract: A processor executes a predetermined operation process by switching a connection structure between a plurality of arithmetic and logic unit modules. Each of the arithmetic and logic unit modules includes a plurality of arithmetic and logic units. The arithmetic and logic unit modules include a first arithmetic and logic unit module that includes a plurality of arithmetic and logic units that executes various operation processes, and a second arithmetic and logic unit module that includes a plurality of arithmetic and logic units of which executable operation processes are limited compared with the first arithmetic and logic unit module.
    Type: Application
    Filed: March 3, 2005
    Publication date: January 5, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Shiro Uriu, Mitsuharu Wakayoshi
  • Publication number: 20060004993
    Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.
    Type: Application
    Filed: February 23, 2005
    Publication date: January 5, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Shiro Uriu, Mitsuharu Wakayoshi, Tetsuo Kawano, Hiroshi Furukawa, Ichiro Kasama, Kazuaki Imafuku, Toshiaki Suzuki
  • Publication number: 20060004980
    Abstract: A plurality of address creators are provided corresponding to a plurality of memories of ALU modules. The address creators create addresses for reading or writing data from the memories each time a connection configuration is switched. In creating addresses in the memories, the address creators enable operations to be set by using various types of parameters and set values by mounting special-purpose hardware for memory ports, so that addresses can be created at high-speed.
    Type: Application
    Filed: January 14, 2005
    Publication date: January 5, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Mitsuharu Wakayoshi, Shiro Uriu
  • Patent number: 6947413
    Abstract: A switching apparatus that is used for high-speed large-capacity routing and a communication apparatus and communication system that are used for an efficient recursive multicast. A matrix switch performs self-routing on a packet on the basis of a tag including output route information set in the packet. Selectors are located so as to correspond to N output ports P#1 through P#N of the matrix switch and perform N-to-one selection control. Setting registers hold selection information used by the selectors to select a signal.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: September 20, 2005
    Assignee: Fujitsu Limited
    Inventors: Tetsuaki Wakabayashi, Kenichi Okabe, Shiro Uriu, Hiroshi Tomonaga, Naoki Matsuoka
  • Patent number: 6789176
    Abstract: In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: September 7, 2004
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Masanobu Furukoshi, Tetsuaki Wakabayashi, Kazumasa Sonoda
  • Publication number: 20030179712
    Abstract: The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S11). The output message identifier MID is reserved (S12), and the tag information and output MID are assigned to the BOM (S13). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S31 and S32). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S41 and S42). Then, the output MID is released (S43).
    Type: Application
    Filed: March 26, 1999
    Publication date: September 25, 2003
    Inventors: YASUSI KOBAYASHI, YOSHIHIRO WATANABE, HIROSHI NISHIDA, MASAMI MURAYAMA, NAOYUKI IZAMA, YASUHIRO ASO, YOSHIHIRO UCHIDA, HIROMI YAMANAKA, JIN ABE, YOSHIHISA TSURUTA, YOSHIHARU KATO, SATOSHI KAKUMA, SHIRO URIU, NORIKO SAMEJIMA, EIJI ISHIOKA, SHIGERU SEKINE, YOSHIYUKI KARAKAWA, ATSUSHI KAGAWA, MIKIO NAKAYAMA, MIYUKI KAWATAKA, SATOSHI ESAKA, NOBUYUKI TSUTSUI, FUMIO HIRASE, ATSUKO SUZUKI, SHOUJI KOHIRA, KENICHI OKABE, TAKASHI HATANO, YASUHIRO NISHIKAWA, JUN ITOH, SHINICHI ARAYA
  • Patent number: 6510165
    Abstract: A service identification adding portion adds service identification information to a cell corresponding to each connection that uses a predetermined communication service (ABR service) and that is input to a switch system. A connection number counting portion counts the number of connections that use the communication service on each output line at predetermined intervals. A band control information generating portion generates band control information corresponding to each output line at predetermined intervals based on the number of connections counted at predetermined intervals. A band control information indicating portion sends band control information at predetermined intervals corresponding to each output line to a transmission side terminal corresponding to a connection that uses the communication service on each output line.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: January 21, 2003
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Norio Suzuki, Noriko Samejima
  • Publication number: 20030002517
    Abstract: A communications apparatus for switching among different interfaces includes a switch unit. The switch unit includes a main switch for switching data of a fixed length and an interface having a first buffer for an input of the main switch and a second buffer for an output of the main switch.
    Type: Application
    Filed: October 30, 2001
    Publication date: January 2, 2003
    Inventors: Ryo Takajitsuko, Kenichi Okabe, Shiro Uriu, Hiroya Kawasaki
  • Publication number: 20020145995
    Abstract: In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.
    Type: Application
    Filed: April 5, 1999
    Publication date: October 10, 2002
    Inventors: SHIRO URIU, MASANOBU FURUKOSHI, TETSUAKI WAKABAYASHI, KAZUMASA SONODA
  • Patent number: 6430157
    Abstract: A switching system in an ATM switching system accommodating an ABR is constructed of an individual units connected to a transmitting terminal or a receiving terminal to implement an efficient bandwidth authorization, and a plurality of intra-system relay devices having transmission allowed rate calculating units. In this switching system, there are separated a transfer of a management cell between the transmitting terminal or the receiving terminal and the individual unit and a transfer of the management cell between the plurality of intra-system relay devices.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: August 6, 2002
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Kazumasa Sonoda, Hiroshi Ishiwata
  • Publication number: 20020080722
    Abstract: A switching system in an ATM switching system accommodating an ABR is constructed of an individual units connected to a transmitting terminal or a receiving terminal to implement an efficient bandwidth authorization, and a plurality of intra-system relay devices having transmission allowed rate calculating units. In this switching system, there are separated a transfer of a management cell between the transmitting terminal or the receiving terminal and the individual unit and a transfer of the management cell between the plurality of intra-system relay devices.
    Type: Application
    Filed: March 25, 1998
    Publication date: June 27, 2002
    Inventors: SHIRO URIU, KAZUMASA SONODA, HIROSHI ISHIWATA