Patents by Inventor Shiro Uriu

Shiro Uriu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020031092
    Abstract: A switching apparatus that is used for high-speed large-capacity routing and a communication apparatus and communication system that are used for an efficient recursive multicast. A matrix switch performs self-routing on a packet on the basis of a tag including output route information set in the packet. Selectors are located so as to correspond to N output ports P#1 through P#N of the matrix switch and perform N-to-one selection control. Setting registers hold selection information used by the selectors to select a signal.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 14, 2002
    Inventors: Tetsuaki Wakabayashi, Kenichi Okabe, Shiro Uriu, Hiroshi Tomonaga, Naoki Matsuoka
  • Publication number: 20020024949
    Abstract: Packets input from input HWs #0 to #3 to a packet switch device are buried in time slots A through D. The packet switch device alternately switches the input packets in units of time slots, and inputs the packets to two 4×4 switches. The 4×4 switches make normal switching, and distribute the packets to respective output ports. Then, the packets output from the two 4×4 switches after being switched are alternately multiplexed, and output to output HWs #0 through #3. By making switching in units of packets as described above, a process overhead is prevented from being increased, and also expansion can be easily made. Besides, hardware scale can be made small.
    Type: Application
    Filed: March 13, 2001
    Publication date: February 28, 2002
    Inventors: Hiroshi Tomonaga, Masakatsu Nagata, Kenichi Kawarai, Naoki Matsuoka, Kenichi Okabe, Shiro Uriu
  • Patent number: 6343102
    Abstract: A peripheral device cable, connected to a peripheral device, integrally incorporates a subscriber link that is a physical line for transmitting subscriber information in synchronization with a highway clock and a control link that is a physical line for transmitting control data in synchronization with the highway clock. A control data converter controls interfacing between the control data transferred over the control link synchronously with the highway clock and control data that a control unit transmits/receives asynchronously with the highway clock. The subscriber link is connected to a switch.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: January 29, 2002
    Assignee: Fujitsu Limited
    Inventors: Masaki Kira, Noriko Samejima, Yoshio Morita, Shiro Uriu
  • Patent number: 6333932
    Abstract: The quality and performance of the connectionless communications system are improved. When a BOM is received, the destination address DA of the L3-PDU stored in the payload of the BOM is retrieved, and the tag information is obtained from the DA (S11). The output message identifier MID is reserved (S12), and the tag information and output MID are assigned to the BOM (S13). Then, the tag information and output MID are written to the table. When a COM is received, the tag information and output MID are retrieved using the MID of the COM as a key, and the information is provided for the COM (S31 and S32). When an EOM is received, the tag information and output MID are retrieved using the MID of the EOM as a key, and the information is provided for the EOM (S41 and S42). Then, the output MID is released (S43).
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: December 25, 2001
    Assignee: Fujitsu Limited
    Inventors: Yasusi Kobayasi, Yoshihiro Watanabe, Hiroshi Nishida, Masami Murayama, Naoyuki Izawa, Yasuhiro Aso, Yoshihiro Uchida, Hiromi Yamanaka, Jin Abe, Yoshihisa Tsuruta, Yoshiharu Kato, Satoshi Kakuma, Shiro Uriu, Noriko Samejima, Eiji Ishioka, Shigeru Sekine, Yoshiyuki Karakawa, Atsushi Kagawa, Mikio Nakayama, Miyuki Kawataka, Satoshi Esaka, Nobuyuki Tsutsui, Fumio Hirase, Atsuko Suzuki, Shouji Kohira, Kenichi Okabe, Takashi Hatano, Yasuhiro Nishikawa, Jun Itoh, Shinichi Araya
  • Patent number: 6078585
    Abstract: Four SR modules are provided in the second stage of a 3-stage MSSR switch. To guarantee the MSSR switch the capacity of 20 Gbps, SR modules are provided in each of the first and third stages of the switch. When the capacity of the MSSR switch is extended from 20 Gbps to 40 Gbps, SR modules are added to both of the first and third stages and connected to the four SR modules in the second stage. To further extend the capacity of the MSSR switch to 60 or 80 Gbps, the SR modules are sequentially added to the first and third stages, and the newly provided SR modules are connected to the four SR modules in the second stage.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: June 20, 2000
    Assignee: Fujitsu Limited
    Inventors: Satoshi Kakuma, Shiro Uriu
  • Patent number: 5958069
    Abstract: A system includes a host, first and second devices which operate as an acting device and a standby device, and a simplex unit controlled by the acting device. Each device is provided with a monitoring unit for monitoring the occurrence of failure, means for notifying the other device of a failure in its own device, and active/standby notification means. The active/standby notification means notifies the simplex unit that its own device is acting or standing by when the device becomes the acting device or standby device in response to a command from the host. Upon a failure in the other device when its own device is standing by, the active/standby notification means notifies the simplex unit that its own device is now an apparent acting device. Upon a failure in its own device when its own device is acting, the active/standby notification means notifies the simplex unit that its own device is now an apparent standby device.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: September 28, 1999
    Assignee: Fujitsu Limited
    Inventors: Hiroya Kawasaki, Masaki Kira, Shiro Uriu, Yukinaga Toyoda, Kazumasa Sonoda
  • Patent number: 5878063
    Abstract: A cell count identifier inserting portion for inserting a cell count identifier into the header portion of a cell is provided at a predetermined position within an exchange and a plurality of cell counting portions for counting a cell into which a cell count identifier is inserted are provided on the downstream side of the cell count identifier inserting portion. A cell loss detecting portion compares the number of cells into which the cell count identifier is inserted with the number of cells counted by each of the cell counting portions, detects cell loss on the basis of the result of the comparisons and specifies the section in which cell loss is caused, if the cell loss is detected.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: March 2, 1999
    Assignee: Fujitsu Limited
    Inventors: Hiroya Kawasaki, Shiro Uriu, Koki Mie, Yukinaga Toyoda, Naoki Fukuda
  • Patent number: 5875177
    Abstract: A sending trunk on the input side of an ATM switch is equipped with a test cell generating section, and a receiving trunk on the output side of the ATM switch is equipped with a test cell detecting section. The test cell generating section includes a unit for setting a test cell identifier in the header of a test cell and a unit for generating pieces of data with regularity in the information field of the test cell. The test cell detecting section includes a unit for detecting the test cell identifier from the header of a cell received and a unit for detecting regularity from data in the information field of the cell received. When a test cell is transmitted, the test cell detecting section evaluates the result of a test on the basis of the result of detection of the test cell identifier from the header of the test cell and the result of detection of the regularity from data in the information field of the test cell.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: February 23, 1999
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Yoshihiro Uchida, Shuji Yoshimura
  • Patent number: 5726987
    Abstract: A congestion-monitor control apparatus monitors a congestion condition of each output highway in an asynchronous transfer mode switching system transferring cells to output highways by using a cell-storage buffer. The apparatus includes a monitor circuit monitoring the number of cells stored in the cell-storage buffer for each output highway at a plurality of timings during a given monitor time interval. The apparatus further includes a first determination circuit comparing the number of times when the number of cells from the monitor circuit is equal to or more than a first threshold value during the given monitor time interval with a second threshold value and determining whether the congestion has occurred in a corresponding output highway based on a comparison result.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: March 10, 1998
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Kenichi Okabe, Satoshi Kakuma
  • Patent number: 5691977
    Abstract: In a data access device for writing into or read from a data conversion table on the basis of a clock signal extracted from a cell being transferred over a line, a clock signal generator of the invention generates a second clock signal which differs from the first clock signal extracted from an incoming cell. A write/read control unit writes data into or reads data for maintenance from the data conversion table on the basis of either the first clock signal or the second clock signal when the line is normal. In the event of the occurrence of a failure in the line, on the other hand, the write/read control circuit permits the data conversion table to be written into or read from for maintenance on the basis of the second clock signal.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: November 25, 1997
    Assignee: Fujitsu Limited
    Inventors: Shuji Yoshimura, Satoshi Kakuma, Masami Murayama, Shiro Uriu, Tadashi Hoshino
  • Patent number: 5675587
    Abstract: A test cell generating section periodically generates a pass determining test cell at preset timing, multiplexes them with user cells from a user line interface, and transmits the result of multiplexing to an ATM exchange. When no user cell is supplied from the user line interface, the test cell generating section transmits only the pass determining test cell to the ATM exchange. A cell determining section determines whether a cell supplied from the ATM exchange is a user cell or test cell, identifies/determines the pass based on information of the test cell and outputs only the user cell to the user line side when the supplied cell is the test cell.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: October 7, 1997
    Assignee: Fujitsu Limited
    Inventors: Yuzo Okuyama, Satoshi Kakuma, Shiro Uriu, Kazuo Hajikano
  • Patent number: 5636222
    Abstract: When broadcast is executed in an ATM mode, a subscriber is assigned a path and a channel as information by a central controller of a switching unit, and the information is added to a cell to be transmitted to the switching unit through a subscriber line. The switching unit comprises the central controller, a tag information adder, and a self-routing switch. The self-routing switch comprises a plurality of input lines and output lines, and unit switches provided for each input line corresponding to each of the output lines. The tag information adder adds routing information for the self-routing switch to a cell to be transmitted to the self-routing switching. The routing information comprises a set of bits corresponding to each output line, and the tag information adder adds to the cell the routing information in which a bit corresponding to an output line for transmitting the cell is set to a predetermined logical value.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: June 3, 1997
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Shuji Yoshimura, Satoshi Kakuma
  • Patent number: 5602826
    Abstract: A test system exactly checks the integrity of data in an ATM system, and generates a test cell of a desired band. In the first aspect of the system in which data stored in an ATM cell are transmitted in an 8-bit parallel format in the ATM system, a test cell generating device connected to an input line outputs a test cell having 1 in all of the eight bits or having zero in all of the eight bits, and the test cell confirming device connected to an output line of the ATM switch detects the above described data. In the second aspect, the test cell generating device provided in an input trunk outputs a test cell of a desired band based on a ratio between two optional integers N and n (N.gtoreq.n), the state of a buffer of the ATM switch is monitored, and a load test is conducted to determine whether or not any cell has been destroyed.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: February 11, 1997
    Assignee: Fujitsu Limited
    Inventors: Shuji Yoshimura, Shiro Uriu, Satoshi Kakuma
  • Patent number: 5561662
    Abstract: A switch interface unit, a monitor unit, and a control system interface unit are connected as external units to a highway to which a subscriber information processing unit is also connected so that a monitoring process, that is, a special study process, can be simplified and a cost charged for the subscriber information processing unit can be prevented from increasing greatly. Furthermore, in an accounting process, accounting parameters are accumulated in an accounting information accumulating unit for variations on compressed source addresses, not on source addresses. As a result, the accounting information accumulating unit, etc. can be realized with normal circuit elements only.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: October 1, 1996
    Assignee: Fujitus Limited
    Inventors: Satoshi Kakuma, Kazuo Hajikano, Masami Murayama, Shuji Yoshimura, Shiro Uriu, Jin Abe
  • Patent number: 5555243
    Abstract: A self-routing exchange which includes switch modules connected in multiple stages. A synchronous transfer mode (STM) circuit switch module, which is capable of changing over a connection relationship between incoming highways and outgoing highways, is provided between the multistage-connected switch modules and self-routing switch modules. Asynchronous transfer mode (ATM) switch modules are provided as switch modules in preceding and succeeding stages of the circuit switching module. In dependence upon the number m of self-routing switch modules, a controller sets, by means of software, the connection relationship between the incoming and outgoing highways in each of space switches incorporated within the circuit switching module. As a result, the total mn-number of incoming highways from the self-routing switch modules are connected to respective ones of mn-number of outgoing highways set by the controller.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: September 10, 1996
    Assignee: Fujitsu Limited
    Inventors: Satoshi Kakuma, Shiro Uriu, Noriko Samejima, Masami Murayama, Noaki Fukuda
  • Patent number: 5555265
    Abstract: A switching path setting system is disposed between an input line connected to switching equipment and a switch. An input interface device allocates a cell to a quality class as tag information corresponding to an identifier of the cell. A quality class buffer stores the cell corresponding to the quality class allocated by the input interface device corresponding to the quality class. A cell is read from the quality class buffer at a band allocated to each quality class.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: September 10, 1996
    Assignee: Fujitsu Limited
    Inventors: Satoshi Kakuma, Shiro Uriu, Noriko Samejima, Kazuo Hajikano
  • Patent number: 5524000
    Abstract: A first terminal unit is connected to a line switch via a set of data lines. A second terminal unit is connected to the first terminal unit via a set of data lines. A third terminal unit is connected to the second terminal unit via a set of data lines. Therefore, the terminals are sequentially connected in series. Cells transmitted to the terminals are multiplexed by each terminal and sequentially transmitted upstream, to the third terminal unit, the second terminal unit, and the first terminal unit together with a token. Since the first terminal unit receives a first identification signal from a switch and a second identification signal from downstream, the first terminal unit recognizes that it is the highest order terminal unit, and sends a cell to the switch after separating the cell from a token which is to be returned downstream.
    Type: Grant
    Filed: July 8, 1993
    Date of Patent: June 4, 1996
    Assignee: Fujitsu Limited
    Inventors: Shuji Yoshimura, Satoshi Kakuma, Shiro Uriu
  • Patent number: 5504742
    Abstract: A broadband ISDN remote multiplexer, which is constructed by separating a subscriber line interfacing section from an ATM exchange and installing the same at a remote location connected via a high-speed transmission line, comprises: a first interface unit for carrying out conversion between a transmitted signal of UNI format, carrying a destination number in its GFC field and transmitted over a transmission medium interconnecting the ATM exchange and the broadband ISDN remote multiplexer, and a first path-control signal that directs a connection within the remote multiplexer in accordance with the destination number; a plurality of subscriber line interface units for terminating respectively the plurality of broadband ISDN subscriber lines; and a multiplexing/demultiplexing unit for making a connection between the first interface unit and each of the subscriber line interface units in accordance with the first path-control signal.
    Type: Grant
    Filed: October 20, 1993
    Date of Patent: April 2, 1996
    Assignee: Fujitsu Limited
    Inventors: Satoshi Kakuma, Shuji Yoshimura, Shiro Uriu, Naoki Fukuda
  • Patent number: 5487063
    Abstract: A cell having an attribute of a point-to-multipoint connection is distributed to each of a number of subscribers using a point-to-multipoint connection distributing switch to be provided in parallel with a point-to-point connection, concentrating and distributing switch. Therefore, a hardware configuration can be simply established. Besides, both a point-to-point connection, and a point-to-multipoint connection can be made only by switching a cell to each switching unit, and a software configuration can thus be simplified.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: January 23, 1996
    Assignee: Fujitsu Limited
    Inventors: Satoshi Kakuma, Shiro Uriu, Shuji Yoshimura, Yasuhiro Aso, Masami Murayama
  • Patent number: 5448720
    Abstract: An information processing system includes a simplex system and a duplex system in which at least two data transmitting systems are provided each capable of being an act system or a standby system. Each data transmitting system has a data acquiring unit. The simplex system includes a controller for controlling a selector to switch between the systems. When in a standby condition, the data acquiring unit of the respective data transmitting system in the duplex system issues an access request signal to a switching signal generating unit provided in the controller of the simplex system to request that the output of the selector be switched from the act system to the standby system in the duplex system. Upon receipt of the access request signal from the data acquiring unit in the standby system, the switching signal generating unit switches the selector to the standby system.
    Type: Grant
    Filed: September 4, 1992
    Date of Patent: September 5, 1995
    Assignee: Fujitsu Limited
    Inventors: Shiro Uriu, Shuji Yoshimura, Yoshihiro Uchida