Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.

Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%.

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

Abstract: The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.

Abstract: A method includes etching a dummy gate to form an opening. A gate dielectric layer is deposited in the opening. A blocking layer is deposited over the gate dielectric layer, wherein the blocking layer has a bottom portion over a bottom of the opening and a sidewall portion over a sidewall of the opening. An adhesive layer is deposited over the bottom portion of the blocking layer. A metal layer is deposited over the adhesive layer, wherein the metal layer is in contact with the sidewall portion of the blocking layer.

Abstract: A structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The isolation structure is embedded in the substrate. The isolation structure has a bottom surface and a sidewall. The liner layer is between the substrate and the isolation. A first portion of the liner layer in contact with the sidewall of the isolation structure has a nitrogen concentration lower than a second portion of the liner layer in contact with the bottom surface of the isolation structure.

Abstract: A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.

Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.

Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes a raised structure, a first gate structure over the raised structure, and a first source/drain structure over the raised structure and adjacent the first gate structure. The first isolation structure surrounds the raised structure and the first source/drain structure of the first transistor. A bottommost surface of the first source/drain structure is spaced apart from a topmost surface of the first isolation structure. The second transistor includes a fin structure, a second gate structure over the raised structure, and a second source/drain structure over the fin structure. The second isolation structure surrounds a bottom of the fin structure of the second transistor. A bottommost surface of the second source/drain structure is in contact with a topmost surface of the second isolation structure.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate and a light sensing region in the semiconductor substrate. The image sensor device also includes a dielectric layer over the semiconductor substrate and a filter partially surrounded by the dielectric layer. The filter has a protruding portion protruding from a bottom surface of the dielectric layer. The image sensor device further includes a shielding layer between the dielectric layer and the semiconductor substrate and surrounding the protruding portion of the filter. In addition, the image sensor device includes a reflective element between the shielding layer and an edge of the light sensing region.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate; forming a gate structure on the substrate; depositing a first dielectric layer over the gate structure; depositing a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect through the first dielectric layer; depositing a conductive layer over the exposed surface of the conductive interconnect; depositing a silicon-containing layer over the conductive layer and the conductive interconnect; and forming a metal silicide layer to be a silicide form of the conductive layer by reacting the conductive layer with silicon in the silicon-containing layer.

Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another.

Abstract: A method of electroplating a metal into a recessed feature is provided, which includes: contacting a surface of the recessed feature with an electroplating solution comprising metal ions, an accelerator additive, a suppressor additive and a leveler additive, in which the recessed feature has at least two elongated regions and a cross region laterally between the two elongated regions, and a molar concentration ratio of the accelerator additive:the suppressor additive:the leveler additive is (8-15):(1.5-3):(0.5-2); and electroplating the metal to form an electroplating layer in the recessed feature. An electroplating layer in a recessed feature is also provided.

Abstract: A method comprises forming an image sensor adjacent to a first side of a substrate, thinning a second side of the substrate, performing a halogen treatment on the second side of the substrate and forming a backside illumination layer on the second side of the substrate.

Abstract: A semiconductor device includes a substrate, at least one layer, a metal adhesive, and a metal structure. The layer is disposed on the substrate. The layer has an opening, and the opening has a bottom surface and at least one sidewall. The metal adhesive is disposed on the bottom surface of the opening while leaving at least a portion of the sidewall of the opening exposed. The metal structure is disposed in the opening and on the metal adhesive.

Abstract: An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.

Abstract: In a method for manufacturing an interconnect structure, a dielectric layer is removed to form a first recess and a second recess. The first recess is below the second recess. A first metal layer is deposited to fill the first recess and a first portion of the second recess. A carbon-containing layer is deposited over the first metal layer to fill a second portion of the second recess, which is over the first portion. A second metal layer is deposited over the carbon-containing layer to fill a third portion of the second recess, which is over the second portion. A carbon concentration of the carbon-containing layer is greater than a carbon concentration of the first metal layer and a carbon concentration of the second metal layer, and the carbon concentration of the first metal layer is substantially the same as the carbon concentration of the second metal layer.

Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.

Abstract: A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and includes a n-type work function metal layer overlying the first high-k dielectric layer. The n-type work function metal layer includes a TiAl (titanium aluminum) alloy, in which an atom ratio of Ti (titanium) to Al (aluminum) is in a range substantially from 1 to 3. The semiconductor device further includes a p-type gate structure over a second semiconductor fin, in which the p-type gate structure is fluorine incorporated includes a p-type work function metal layer overlying the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), in which an atom ratio of Ti to N (nitrogen) is in a range substantially from 1:0.9 to 1:1.1.