Abstract: A system for reflowing a semiconductor workpiece including a stage, a first vacuum module and a second vacuum module, and an energy source is provided. The stage includes a base and a protrusion connected to the base, the stage is movable along a height direction of the stage relative to the semiconductor workpiece, the protrusion operably holds and heats the semiconductor workpiece, and the protrusion includes a first portion and a second portion surrounded by and spatially separated from the first portion. The first vacuum module and the second vacuum module respectively coupled to the first portion and the second portion of the protrusion, and the first vacuum module and the second vacuum module are operable to respectively apply a pressure to the first portion and the second portion. The energy source is disposed over the stage to heat the semiconductor workpiece held by the protrusion of the stage.

Abstract: A display device includes a pixel circuit and a stage of a scan driver. The stage of the scan driver is electrically coupled to the pixel circuit. The stage of the scan driver is configured to output a first scan signal and a second scan signal to the pixel circuit. A first enable voltage of the first scan signal is at a first logic level, and a first disable voltage of the first scan signal is at a second logic level. A second enable voltage of the second scan signal is at the second logic level.

Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.

Abstract: A method and an electronic apparatus for predictive value decision and a computer-readable recording medium thereof are provided. First, a model operation interface is activated, and in response to receiving an operation through the model operation interface, the following steps are executed. A shipment predictive value at a target time point is calculated based on historical shipment data. Next, a change ratio scale corresponding to the target time point is calculated using the shipment predictive value corresponding to the target time point and multiple previous shipment predictive values at multiple time points before the target time point. Moreover, an average value of past change ratio scales corresponding to the target time point is calculated based on the historical shipment data. Finally, predictive performance information is provided based on the average value of the past change ratio scales and the change ratio scale corresponding to the target time point.

Abstract: A semiconductor tester and a method for calibrating a probe card and a device under testing (DUT) are disclosed. The semiconductor tester includes: a support platform, including a support surface and configured to be able to move along a direction parallel to the support surface and rotate around a rotating shaft perpendicular to the support surface; a probe card including a plurality of probes stretching towards the support platform; and an alignment assembly, including: at least two first laser emitting apparatuses emitting a plurality of first laser beams; and a second laser emitting apparatus emitting a plurality of second laser beams. The first laser beams and the second laser beams are perpendicular to each other and are each arranged sequentially along a direction perpendicular to the support surface. The semiconductor tester aligns a probe card to a DUT with improved accuracy, thereby preventing the damage to the probe card.

Abstract: Embodiments of the present disclosure provide a memory detection method and detection apparatus, for detecting a current-leakage bitline. The method includes: a memory including a plurality of memory cells, a plurality of sense amplifiers, and the sense amplifier including a power line providing a low potential voltage and a power line providing a high potential voltage; writing first memory data to each of the memory cells; performing a reading operation after the first memory data is written; acquiring a first test result based on a difference between first real data and the first memory data; performing the reading operation again to read second real data in each of the memory cells; acquiring a second test result based on a difference between the second real data and second memory data; and acquiring a specific position of the current-leakage bitline based on the second test result and the first test result.

Abstract: Embodiments of the present disclosure provide a memory detection method and detection apparatus, for detecting a current-leakage bitline. The method includes: a memory including a plurality of memory cells, a plurality of sense amplifiers, and the sense amplifier including a power line providing a low potential voltage and a power line providing a high potential voltage; writing first memory data to each of the memory cells; performing a reading operation after the first memory data is written; acquiring a first test result based on a difference between first real data and the first memory data; performing the reading operation again to read second real data in each of the memory cells; acquiring a second test result based on a difference between the second real data and second memory data; and acquiring a specific position of the current-leakage bitline based on the second test result and the first test result.

Abstract: A data channel aging circuit, a memory, a data channel aging method, and a memory aging method are provided. The data channel aging circuit includes: a memory cell storing a voltage switching signal configured to provide a target voltage state for each of a plurality of data channels in an integrated circuit (IC); a control unit configured to generate a voltage control signal and to send the voltage control signal to each data channel; and a strobe unit configured to switch a conductive state of each data channel based on the voltage switching signal, and to adjust a voltage level of each data channel through the voltage control signal to induce voltage stress aging. The data channel aging circuit improves the reliability of the aging test and the operational stability of the IC products that have went through the aging test.

Abstract: In accordance with the present invention, the single gene SERPINA1 has been identified as a significant predictor of survival in ER+ and ER+/HER2+ breast cancer patients. For example, patients with ER+/FIER2+ breast cancer generally have a worse outcome compared to ER+/FIER2? and ER?/FIER2+ patients. Currently there is no known predictive marker for the treatment C outcome of ER+ and ER+/FIER2+ breast cancers, thus the ability of SERPINA1 to predict the survival of this intrinsic subtype of breast cancer patients is valuable.

Abstract: A semiconductor tester and a method for calibrating a probe card and a device under testing (DUT) are disclosed. The semiconductor tester includes: a support platform, including a support surface and configured to be able to move along a direction parallel to the support surface and rotate around a rotating shaft perpendicular to the support surface; a probe card including a plurality of probes stretching towards the support platform; and an alignment assembly, including: at least two first laser emitting apparatuses emitting a plurality of first laser beams; and a second laser emitting apparatus emitting a plurality of second laser beams. The first laser beams and the second laser beams are perpendicular to each other and are each arranged sequentially along a direction perpendicular to the support surface. The semiconductor tester aligns a probe card to a DUT with improved accuracy, thereby preventing the damage to the probe card.

Abstract: A data channel aging circuit, a memory, a data channel aging method, and a memory aging method are provided. The data channel aging circuit includes: a memory cell storing a voltage switching signal configured to provide a target voltage state for each of a plurality of data channels in an integrated circuit (IC); a control unit configured to generate a voltage control signal and to send the voltage control signal to each data channel; and a strobe unit configured to switch a conductive state of each data channel based on the voltage switching signal, and to adjust a voltage level of each data channel through the voltage control signal to induce voltage stress aging. The data channel aging circuit improves the reliability of the aging test and the operational stability of the IC products that have went through the aging test.

Abstract: The disclosure provides a display, a method for monitoring played content and a system using the same method. The method includes: capturing a played screen of a multimedia content at a specified timing point; using a first feature extracting model to transform the played screen to a played screen feature sequence; determining whether the reference screen feature sequence corresponding to the specified time point matches the played screen feature sequence; if yes, determining the multimedia contents have been correctly played, and vice versa.

Abstract: The disclosure provides a display, a method for monitoring played content and a system using the same method. The method includes: capturing a played screen of a multimedia content at a specified timing point; using a first feature extracting model to transform the played screen to a played screen feature sequence; determining whether the reference screen feature sequence corresponding to the specified time point matches the played screen feature sequence; if yes, determining the multimedia contents have been correctly played, and vice versa.

Abstract: In accordance with the present invention, the single gene SERPINA1 has been identified as a significant predictor of survival in ER+ and ER+/HER2+ breast cancer patients. For example, patients with ER+/FIER2+ breast cancer generally have a worse outcome compared to ER+/FIER2? and ER?/FIER2+ patients. Currently there is no known predictive marker for the treatment C outcome of ER+ and ER+/FIER2+ breast cancers, thus the ability of SERPINA1 to predict the survival of this intrinsic subtype of breast cancer patients is valuable.

Abstract: A method for forming a lithography mask includes forming a capping layer on a reflective multilayer layer, the capping layer comprising a first material, forming a patterned patterning layer on the capping layer, and introducing a secondary material into the capping layer, the secondary material having an atomic number that is smaller than 15.

Abstract: Disclosed are compositions for treating an estrogen receptor (ER) or estrogen related receptor (ERR) mediated disorder, comprising a therapeutically effective amount of a compound selected from the group consisting of Compound Nos. 1-9, 7-2, 7-4, 7-5, 7-7, 7-8, 8-2 and 3-15 set forth herein or a pharmaceutically acceptable salt thereof, wherein said compound modulates estrogen receptors and/or estrogen-related receptors and methods for use of said compositions.

Abstract: A polyimide is provided. The polyimide includes a repeating unit represented by formula 1.

Abstract: A method for forming a lithography mask includes forming a capping layer on a reflective multilayer layer, the capping layer comprising a first material, forming a patterned patterning layer on the capping layer, and introducing a secondary material into the capping layer, the secondary material having an atomic number that is smaller than 15.

Abstract: A method for forming a lithography mask includes forming a capping layer on a reflective multilayer layer, the capping layer comprising a first material, forming a patterned patterning layer on the capping layer, and introducing a secondary material into the capping layer, the secondary material having an atomic number that is smaller than 15.

Abstract: One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.