Abstract: A high quality factor on-package, off-die inductor assembly is disclosed. The assembly includes a flip-chip, ball-grid array package substrate, an on-package, off-die trace line is coupled to one or more bumps attached to an upper surface of the package substrate. The trace line has a self-inductance and a predetermined length. The quality factor associated with the inductor is a ratio of the trace line's inductance to the trace lines resistance. The package substrate is a low loss laminate.

Abstract: A high quality factor on-package, off-die inductor assembly is disclosed. The assembly includes a flip-chip, ball-grid array package substrate, an on-package, off-die trace line is coupled to one or more bumps attached to an upper surface of the package substrate. The trace line has a self-inductance and a predetermined length. The quality factor associated with the inductor is a ratio of the trace line's inductance to the trace lines resistance. The package substrate is a low loss laminate.

Abstract: Disclosed is a routing algorithm that uses a new concept of node metric system for optimizing the throughput of a network, in particular, a shared medium network. The measure of congestion of a path in the network is represented by a path metric which is computed by summing the node metrics of the intermediate nodes on the path. Factors used in computing node metrics include the following: 1. future traffic load from neighboring nodes to the node; and 2. future traffic load from the node to the neighboring nodes.

Abstract: A method and apparatus for generating a first clock signal and a second time staggered clock signal; and driving a first circuit with the first clock signal and a second circuit with the second time staggered clock signal, to cause unwanted signals due to the first clock signal and unwanted signals due to the second time staggered clock signal to occur at frequencies that are a multiple of the first clock frequency. The method and apparatus further comprising synchronizing outputs from the first circuit and the second circuit to facilitate transfer of information therebetween.

Abstract: A method and apparatus for generating a first clock signal and a second time staggered clock signal; and driving a first circuit with the first clock signal and a second circuit with the second time staggered clock signal, to cause unwanted signals due to the first clock signal and unwanted signals due to the second time staggered clock signal to occur at frequencies that are a multiple of the first clock frequency. The method and apparatus further comprising synchronizing outputs from the first circuit and the second circuit to facilitate transfer of information therebetween.

Abstract: An electronic attenuator device is provided whose attenuation characteristics are substantially insensitive to variations in component element parameters and ambient temperature changes. Advantageously, an attenuator device made according to the present invention may be constructed at substantially reduced cost without loss of attenuation precision.