Abstract: A method for manufacturing a semiconductor device includes preparing a plurality of semiconductor elements, preparing a support member, attaching the plurality of semiconductor elements to the support member so that second surfaces of the plurality of semiconductor elements face the support member, encapsulating the plurality of semiconductor elements with an encapsulation material, removing the support member from an encapsulation material layer in which the plurality of semiconductor elements is encapsulated with the encapsulation material, bonding a first protective film to a second surface of the encapsulation material layer located on the second surface side of the plurality of semiconductor elements, and forming a re-distribution layer on a first surface of the encapsulation material layer located on the first surface side of the plurality of semiconductor elements after bonding the first protective film to the encapsulation material layer.

Abstract: A video display apparatus includes: an area-specific lighting value calculator configured to calculate a lighting value of each of divided light source regions of a backlight and output the lighting value as numerical data; a signal output module configured to output a video signal correlated with the lighting value to a display module; a backlight controller configured to control the backlight based on the lighting value; a correction gain setting module configured to obtain a signal correction coefficient; a frequency separator configured to separate the input video signal; a signal corrector configured to correct the lighting value with respect to a low frequency component or DC component separated from the input video signal to suppress amplification of noise contained in a dark portion and generate an output video signal; and a display controller configured to control the display module to display the output video signal.

Abstract: An inter-field pull-down pattern detecting circuit determines whether an input video signal is a first pull-down signal or a second pull-down signal, on the basis of input plug information and a pattern of the consecutive inter-field correlation levels, obtained from an inter-field correlation determination circuit. A counter counts the number of times the pattern detecting circuit determines that the input video signal is the first pull-down signal. The counter is reset to “0” when the input video signal is determined to be other than the first and second pull-down signals. When the count of the counter exceeds a preset value, the input video signal is finally determined to be the first pull-down signal.

Abstract: According to one embodiment, a motion detection correction module is provided which corrects the result of detection by a motion detector, which detects motion in one frame on a pixel-by-pixel basis, for each of small regions obtained by dividing the entire picture on the basis of the result of detection by a picture-based illumination component variation detector that detects interfield illumination component variations on a picture-by-picture basis and the result of detection by a block-based illumination component variation detector that detects interfield illumination component variations on a small-region-by-small-region basis.

Abstract: According to one embodiment, a video display apparatus is provided. The video display apparatus includes: a margin generating module which adds a peripheral margin to an input first 3D image signal for generating a 3D image in a case where the first 3D image signal has no peripheral margin; and a 3D image generating module which compensates for a second 3D image signal in the margin, generates the 3D image based on the first and second 3D image signals, and outputs the 3D image to a video display unit.

Abstract: According to one embodiment, there is provided a video display apparatus, including: a 3D image generating module configured to receive a 3D image input signal; and to generate a 3D image display signal to be displayed on a screen of a video display unit, from the 3D image input signal; and an image mixing module configured to receive a 2D image signal and the 3D image display signal; to mix the 3D image display signal to be displayed on a first area of the screen and the 2D image signal to be displayed on a second area of the screen to generate a mixed image signal, the first area being different from the second area; and to output the mixed image signal to the video display unit.

Abstract: An image processor includes: an receiving module configured to receive a video signal of a content; an image quality adjusting module configured to adjust image quality of the video signal received by the receiving module using image quality adjustment parameters including at least a contrast-related parameter; a 3D video detecting module configured to determine whether the video signal is of a 3D content; and a control module configured to control the image quality adjusting module to adjust the image quality of the video signal using the contrast-related parameter being set to a second parameter setting for enhancing contrast more than at a first parameter setting, when the video signal is determined to be the 3D content by the 3D video detecting module while the image quality adjusting module is adjusting the image quality using the contrast-related parameter being set at the first parameter setting.

Abstract: According to one embodiment, an image processing circuit comprising first memory unit which stores image signal, equalizing circuit which, when there is no movement between two picture signals, outputs average signal between the both signals, second memory unit which stores the average signal, pull-down detecting circuit which outputs pull-down interpolation signal for deinterlacing process from a plurality of frames of the pull-down signals when it is determined that the picture signal is based on the pull-down signals upon receipt of the average signal, an output from the second memory unit, and output from the first memory unit, interpolation signal generating circuit which generates interpolation signal, the outputs from the first and second memory units, and noninterlaced scanning conversion circuit which generates noninterlaced signal by adding the pull-down signals to the output from the second memory unit when the picture signal based on the pull-down signals.

Abstract: According to one embodiment, an apparatus includes an average calculation portion which performs a average calculating process between frames by use of an input signal and one-frame delay signal and acquires an output signal having cross color and dot disturbance components reduced, and an up-convert signal detecting portion which sets the inter-frame mean delay processing portion into an operative state when the input signal is an up-convert signal obtained by up-converting a low-resolution signal into a high-resolution signal.

Abstract: A video display apparatus includes: an area-specific lighting value calculator configured to calculate a lighting value of each of divided light source regions of a backlight and output the lighting value as numerical data; a signal output module configured to output a video signal correlated with the lighting value to a display module; a backlight controller configured to control the backlight based on the lighting value; a correction gain setting module configured to obtain a signal correction coefficient; a frequency separator configured to separate the input video signal; a signal corrector configured to correct the lighting value with respect to a low frequency component or DC component separated from the input video signal to suppress amplification of noise contained in a dark portion and generate an output video signal; and a display controller configured to control the display module to display the output video signal.

Abstract: An image processor includes: an receiving module configured to receive a video signal of a content; an image quality adjusting module configured to adjust image quality of the video signal received by the receiving module using image quality adjustment parameters including at least a contrast-related parameter; a 3D video detecting module configured to determine whether the video signal is of a 3D content; and a control module configured to control the image quality adjusting module to adjust the image quality of the video signal using the contrast-related parameter being set to a second parameter setting for enhancing contrast more than at a first parameter setting, when the video signal is determined to be the 3D content by the 3D video detecting module while the image quality adjusting module is adjusting the image quality using the contrast-related parameter being set at the first parameter setting.

Abstract: According to one embodiment, a signal processor includes: a signal input module configured to receive an interlaced-to-progressive following field signal of a predetermined video; a first field delay module configured to delay the following field signal by one field to generate a current field signal; a second field delay module configured to delay the current field signal by one field to generate a preceding field signal; a motion detector configured to detect inter-frame motion for each interpolation target pixel based on the following field signal and the preceding field signal, the interpolation target pixel being a missing pixel within scan lines displaying the video; a boundary specifying module configured to specify a boundary between a moving-image area and a still-image area of the video based on the inter-frame motion; an interpolation pixel generator configured to generate an interpolation pixel that interpolates the interpolation target pixel based on the boundary and at least one of the following

Abstract: According to one embodiment, a de-interlacing apparatus includes: a motion vector detecting section; a full-screen shift detecting section detecting a full-screen shift; a moving-or-still judging section performing a moving/still judgment for a video signal; a moving judgment correcting section correcting a moving/still judgment result to lean toward a moving judgment when full-screen shift is detected; a first interpolation signal generating section generating a first interpolation signal for interpolating a one-field delay signal based on the motion vector and the full-screen shift; a second interpolation signal generating section generating a second interpolation signal for interpolating the one-field delay signal from a current field signal or a two-field delay signal; and an interpolation signal mixing section mixing the first and second interpolation signals to generate a mixed interpolation signal.

Abstract: According to one embodiment, a motion detection correction module is provided which corrects the result of detection by a motion detector, which detects motion in one frame on a pixel-by-pixel basis, for each of small regions obtained by dividing the entire picture on the basis of the result of detection by a picture-based illumination component variation detector that detects interfield illumination component variations on a picture-by-picture basis and the result of detection by a block-based illumination component variation detector that detects interfield illumination component variations on a small-region-by-small-region basis.

Abstract: According to one embodiment, a de-interlacing apparatus includes: a motion vector detecting section; a full-screen shift detecting section detecting a full-screen shift; a moving-or-still judging section performing a moving/still judgment for a video signal; a moving judgment correcting section correcting a moving/still judgment result to lean toward a moving judgment when full-screen shift is detected; a first interpolation signal generating section generating a first interpolation signal for interpolating a one-field delay signal based on the motion vector and the full-screen shift; a second interpolation signal generating section generating a second interpolation signal for interpolating the one-field delay signal from a current field signal or a two-field delay signal; and an interpolation signal mixing section mixing the first and second interpolation signals to generate a mixed interpolation signal.

Abstract: It is an object of the invention to provide an aberration correcting mirror which has a small size, power saving, a low voltage, a low price and high precision. In particular, it is an object to provide a practical mirror for correcting a spherical aberration.

Abstract: An inter-field pull-down pattern detecting circuit determines whether an input video signal is a first pull-down signal or a second pull-down signal, on the basis of input plug information and a pattern of the consecutive inter-field correlation levels, obtained from an inter-field correlation determination circuit. A counter counts the number of times the pattern detecting circuit determines that the input video signal is the first pull-down signal. The counter is reset to “0” when the input video signal is determined to be other than the first and second pull-down signals. When the count of the counter exceeds a preset value, the input video signal is finally determined to be the first pull-down signal.

Abstract: According to one embodiment, an image processing circuit comprising first memory unit which stores image signal, equalizing circuit which, when there is no movement between two picture signals, outputs average signal between the both signals, second memory unit which stores the average signal, pull-down detecting circuit which outputs pull-down interpolation signal for deinterlacing process from a plurality of frames of the pull-down signals when it is determined that the picture signal is based on the pull-down signals upon receipt of the average signal, an output from the second memory unit, and output from the first memory unit, interpolation signal generating circuit which generates interpolation signal, the outputs from the first and second memory units, and noninterlaced scanning conversion circuit which generates noninterlaced signal by adding the pull-down signals to the output from the second memory unit when the picture signal based on the pull-down signals.

Abstract: A piezoelectric actuator is constructed by forming a common electrode 27 of Cr, a piezoelectric layer 29 of Pb(Zr,Ti)O3, a cover layer 31 of BaTiO3, and an individual electrode 33 of Pt in this order into a laminate. The thickness of the piezoelectric layer 29 in the lamination direction (T1) and the thickness of the cover layer 31 in the lamination direction (T2) satisfy the relationship of 0.08?T2/T1?1. The relative dielectric constant of the piezoelectric layer 29 (?r1) and the relative dielectric constant of the cover layer 31 (?r2) satisfy the relationship of ?r2/?r1?0.2.

Abstract: A piezoelectric actuator 21 has: a piezoelectric actuator part 22 made up of a common electrode 27, a piezoelectric element 29, and an individual electrode 33; an electrical interconnection joint part 43 formed on the individual electrode 33; an electrical interconnection 45 formed on the electrical interconnection joint part 43; a head block 47 fixed to a nozzle plate 39 through the electrical interconnection 45; and a PI tape 49 disposed within the head block 47. A closed space 57 is defined between the head block 47 and the nozzle plate 39. The closed space 57 is divided by the PI tape 49 into two sections. Of these two sections of the closed space 57, the one on the side of the head block 47 constitutes a first closed space 57a. A moisture absorbent 52 is sealed within the first closed space 57a. Relative humidity within the closed space 57 of the ink jet head 1 is not less than 0% nor more than 20%.