Patents by Inventor Shogo Murashige

Shogo Murashige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230130571
    Abstract: An organic EL display device has a frame region provided with a first dam wall and a second dam wall to surround a display region. The first dam wall and the second dam wall include: a first resin wall layer; a first conductive wall layer covering the first resin wall layer; a second resin wall layer over the first resin wall layer through the first conductive wall layer; and a second conductive wall layer covering the second resin wall layer. The second resin wall layer is positioned between: a step portion included in the first conductive wall layer and covering a peripheral end face of the first resin wall layer; and a portion included in the second conductive wall layer and corresponding to the step portion of the first conductive wall layer.
    Type: Application
    Filed: April 10, 2020
    Publication date: April 27, 2023
    Inventors: SHOGO MURASHIGE, YUJIRO TAKEDA
  • Publication number: 20230090537
    Abstract: A TFT layer is provided that includes a stack of, in sequence, display wires, a protective film, a first flattening film, a metal wire layer and a second flattening film; further, a frame region has a first trench and a second trench respectively provided in the first flattening film and the second flattening film and overlapping the display wires; further, a second electrode is provided to cover the first trench and the second trench; further the protective film includes a first protective film and a third protective film formed of a silicon oxide film, and a second protective film formed of a silicon nitride film.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 23, 2023
    Inventors: Hirohide MIMURA, SHOGO MURASHIGE, YUJIRO TAKEDA
  • Patent number: 11145766
    Abstract: An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 12, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yujiro Takeda, Hiroshi Matsukizono, Akihiro Oda, Shogo Murashige, Kohhei Tanaka
  • Patent number: 11043600
    Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT supported by the substrate. The oxide semiconductor TFT includes an oxide semiconductor layer containing In, Ga, and Zn, a gate electrode, a gate insulating layer formed between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode that are in contact with the oxide semiconductor layer. The oxide semiconductor layer has a layered structure that includes a first layer, a second layer, and an intermediate transition layer disposed between the first layer and the second layer, and the first layer is disposed closer to the gate insulating layer side than the second layer. The first layer and the second layer have different compositions, and the intermediate transition layer has a continuously changing composition from the first layer side toward the second layer side.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 22, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Nakajima, Hirohiko Nishiki, Yujiro Takeda, Shogo Murashige
  • Patent number: 11028270
    Abstract: [Problem] To provide a composition for a black matrix which is a material suitable for manufacturing a black matrix, which is suitable for a high luminance display device structure and has high heat resistance and high light-shielding properties. [Means for Solution] The present invention uses a composition for a black matrix comprising: (I) a black colorant containing carbon black having a volume average particle diameter of 1 to 300 nm; (II) a siloxane polymer to be obtained by hydrolyzing and condensing a silane compound represented by a prescribed formula in the presence of an acidic or basic catalyst; (III) surface modified silica fine particles; (IV) a thermal base generator; and (V) a solvent.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: June 8, 2021
    Assignee: Merck Patent GmbH
    Inventors: Hirohiko Nishiki, Tohru Okabe, Izumi Ishida, Shogo Murashige, Atsuko Noya, Toshiaki Nonaka, Naofumi Yoshida
  • Publication number: 20210135013
    Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT supported by the substrate. The oxide semiconductor TFT includes an oxide semiconductor layer containing In, Ga, and Zn, a gate electrode, a gate insulating layer formed between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode that are in contact with the oxide semiconductor layer. The oxide semiconductor layer has a layered structure that includes a first layer, a second layer, and an intermediate transition layer disposed between the first layer and the second layer, and the first layer is disposed closer to the gate insulating layer side than the second layer. The first layer and the second layer have different compositions, and the intermediate transition layer has a continuously changing composition from the first layer side toward the second layer side.
    Type: Application
    Filed: December 15, 2017
    Publication date: May 6, 2021
    Inventors: Shinji NAKAJIMA, Hirohiko NISHIKI, Yujiro TAKEDA, Shogo MURASHIGE
  • Patent number: 10991725
    Abstract: An active matrix substrate includes: a substrate (1); a peripheral circuit including a plurality of first TFTs (10); and a plurality of second TFTs (20), wherein each of the first and second TFTs (10, 20) includes: a gate electrode (3A, 3B); a gate insulating layer (5); an oxide semiconductor layer (7A, 7B) including a channel region (7Ac, 7Bc), a source contact region (7As, 7Bs) and a drain contact region (7Ad, 7Bd), wherein the source contact region and the drain contact region are located on opposite sides of the channel region; a source electrode (8A, 8B) that is in contact with the source contact region and a drain electrode (9A, 9B) that is in contact with the drain contact region; the oxide semiconductor layer of the first TFTs and the second TFTs is formed from the same oxide semiconductor film; a carrier concentration in the channel regions (7Ac) of the first TETs is higher than a carrier concentration in the channel regions (7Bc) of the second TETs.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: April 27, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Akihiro Oda, Yujiro Takeda, Shogo Murashige, Hiroshi Matsukizono
  • Patent number: 10879064
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Nakajima, Hirohiko Nishiki, Hirohide Mimura, Yuhichi Saitoh, Yujiro Takeda, Shogo Murashige, Izumi Ishida, Tohru Okabe
  • Publication number: 20200277494
    Abstract: [Problem] To provide a composition for a black matrix which is a material suitable for manufacturing a black matrix, which is suitable for a high luminance display device structure and has high heat resistance and high light-shielding properties. [Means for Solution] The present invention uses a composition for a black matrix comprising: (I) a black colorant containing carbon black having a volume average particle diameter of 1 to 300 nm; (II) a siloxane polymer to be obtained by hydrolyzing and condensing a silane compound represented by a prescribed formula in the presence of an acidic or basic catalyst; (III) surface modified silica fine particles; (IV) a thermal base generator; and (V) a solvent.
    Type: Application
    Filed: December 7, 2017
    Publication date: September 3, 2020
    Inventors: Hirohiko NISHIKI, TOHRU OKABE, IZUMI ISHIDA, SHOGO MURASHIGE, Atsuko NOYA, Toshiaki NONAKA, Naofumi YOSHIDA
  • Publication number: 20200243568
    Abstract: An active matrix substrate includes: a substrate (1); a peripheral circuit including a plurality of first TFTs (10); and a plurality of second TFTs (20), wherein each of the first and second TFTs (10, 20) includes: a gate electrode (3A, 3B); a gate insulating layer (5); an oxide semiconductor layer (7A, 7B) including a channel region (7Ac, 7Bc), a source contact region (7As, 7Bs) and a drain contact region (7Ad, 7Bd), wherein the source contact region and the drain contact region are located on opposite sides of the channel region; a source electrode (8A, 8B) that is in contact with the source contact region and a drain electrode (9A, 9B) that is in contact with the drain contact region; the oxide semiconductor layer of the first TFTs and the second TFTs is formed from the same oxide semiconductor film; a carrier concentration in the channel regions (7Ac) of the first TETs is higher than a carrier concentration in the channel regions (7Bc) of the second TETs.
    Type: Application
    Filed: March 2, 2018
    Publication date: July 30, 2020
    Inventors: Akihiro ODA, Yujiro TAKEDA, Shogo MURASHIGE, Hiroshi MATSUKIZONO
  • Patent number: 10690975
    Abstract: Provided are an active-matrix substrate, a method for manufacturing the same, and a display device, which render it possible to inhibit electrostatic discharge from occurring during the process of manufacturing a display panel and suppress manufacturing cost. An IGZO film, which is positioned between a silicon oxide film included in a gate insulating film and an etch-stop layer, is annealed at 200 to 350° C. after a passivation film for protecting a TFT is formed. As a result, the passivation film is annealed, and the IGZO film is changed from a conductor to a semiconductor. Consequently, it is not only possible to suppress the occurrence of ESD, but also possible to eliminate the need to sever an electrostatic discharge prevention circuit from a display panel, resulting in a reduced cost of manufacturing a display device.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 23, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Shinji Nakajima, Izumi Ishida, Shogo Murashige
  • Publication number: 20200194254
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 18, 2020
    Inventors: Shinji NAKAJIMA, Hirohiko NISHIKI, Hirohide MIMURA, Yuhichi SAITOH, Yujiro TAKEDA, Shogo MURASHIGE, Izumi ISHIDA, Tohru OKABE
  • Patent number: 10685598
    Abstract: A wiring delay is prevented or reduced by lowering a wiring resistance without making a wire wider. The present invention includes: a light blocking film (102); a light-transmitting film (106); and a first wiring layer (105A) which serves as part of a wire configured to electrically control an amount of transmitted light for each pixel, the first wiring layer (105A) being provided over the light blocking film (102), and the light-transmitting film (106) being provided over the first wiring layer (105A) so as to cover a side surface of the first wiring layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 16, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Shinji Nakajima, Izumi Ishida, Shogo Murashige
  • Publication number: 20200152802
    Abstract: An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer.
    Type: Application
    Filed: June 4, 2018
    Publication date: May 14, 2020
    Inventors: Yujiro TAKEDA, Hiroshi MATSUKIZONO, Akihiro ODA, Shogo MURASHIGE, Kohhei TANAKA
  • Patent number: 10529743
    Abstract: Disclosed is an active matrix substrate that includes a plurality of TFTs. The active matrix substrate 11 includes a substrate 100, TFTs, a light transmission film 204, and a protection film Cap4. The TFTs are provided on the substrate 100 so as to correspond to a plurality of pixels, respectively. The light transmission film 204 is provided between the TFTs and the substrate 100. The protection film Cap4 covers an end surface 204b of the light transmission film 204, the end surface 204b being not parallel with the substrate 100. The TFT includes a gate electrode, a gate insulating film, a semiconductor film, a drain electrode, and a source electrode. The protection film Cap4 is arranged between the light transmission film 204 and the semiconductor film of the TFT.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shogo Murashige, Izumi Ishida, Tomohiro Kosaka, Tohru Okabe, Takeshi Hara, Hirohiko Nishiki
  • Publication number: 20190113813
    Abstract: Provided are an active-matrix substrate, a method for manufacturing the same, and a display device, which render it possible to inhibit electrostatic discharge from occurring during the process of manufacturing a display panel and suppress manufacturing cost. An IGZO film, which is positioned between a silicon oxide film included in a gate insulating film and an etch-stop layer, is annealed at 200 to 350° C. after a passivation film for protecting a TFT is formed. As a result, the passivation film is annealed, and the IGZO film is changed from a conductor to a semiconductor. Consequently, it is not only possible to suppress the occurrence of ESD, but also possible to eliminate the need to sever an electrostatic discharge prevention circuit from a display panel, resulting in a reduced cost of manufacturing a display device.
    Type: Application
    Filed: March 24, 2017
    Publication date: April 18, 2019
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Shinji NAKAJIMA, Izumi ISHIDA, Shogo MURASHIGE
  • Publication number: 20190103052
    Abstract: A wiring delay is prevented or reduced by lowering a wiring resistance without making a wire wider. The present invention includes: a light blocking film (102); a light-transmitting film (106); and a first wiring layer (105A) which serves as part of a wire configured to electrically control an amount of transmitted light for each pixel, the first wiring layer (105A) being provided over the light blocking film (102), and the light-transmitting film (106) being provided over the first wiring layer (105A) so as to cover a side surface of the first wiring layer.
    Type: Application
    Filed: March 27, 2017
    Publication date: April 4, 2019
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Shinji NAKAJIMA, Izumi ISHIDA, Shogo MURASHIGE
  • Publication number: 20190081081
    Abstract: Disclosed is an active matrix substrate that includes a plurality of TFTs. The active matrix substrate 11 includes a substrate 100, TFTs, a light transmission film 204, and a protection film Cap4. The TFTs are provided on the substrate 100 so as to correspond to a plurality of pixels, respectively. The light transmission film 204 is provided between the TFTs and the substrate 100. The protection film Cap4 covers an end surface 204b of the light transmission film 204, the end surface 204b being not parallel with the substrate 100. The TFT includes a gate electrode, a gate insulating film, a semiconductor film, a drain electrode, and a source electrode. The protection film Cap4 is arranged between the light transmission film 204 and the semiconductor film of the TFT.
    Type: Application
    Filed: July 7, 2016
    Publication date: March 14, 2019
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: SHOGO MURASHIGE, IZUMI ISHIDA, TOMOHIRO KOSAKA, TOHRU OKABE, TAKESHI HARA, HIROHIKO NISHIKI
  • Patent number: 10209592
    Abstract: An active matrix substrate includes an insulating substrate in which light-transmitting areas and a light-shielding area are formed. The active matrix substrate further includes: a light-shielding film formed in the light-shielding area on the insulating substrate, with a transparent base material containing carbon particles, the light shielding film being colored with the carbon particles; an inorganic film formed on the light-shielding film; light-transmitting films formed in the light-transmitting areas on the insulating substrate, with a transparent base material containing transparent oxidized carbon particles; gate lines provided on the inorganic film; a gate insulating film provided on the gate lines; thin film transistors provided in matrix on the gate insulating film; and data lines provided on the light-shielding film to intersect with the gate lines. The data lines are electrically connected with the thin film transistors.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 19, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Hara, Tomohiro Kosaka, Izumi Ishida, Shogo Murashige
  • Publication number: 20180254293
    Abstract: An active matrix substrate 10 includes: an insulating substrate 110; a first conductive film 130 formed on the insulating substrate 110; a light-transmitting film 114 formed on the insulating substrate 110 so that the light-transmitting film 114 covers the first conductive film 130; a second conductive film 140 formed on the light-transmitting film 114; a first insulating layer 115 formed on the light-transmitting film 114 so that the first insulating layer 115 covers the second conductive film 140; a semiconductor film 170 formed on the first insulating layer 115; and a third conductive film 150 formed on the first insulating layer 115 and the semiconductor film 170. The first conductive film 130 and the second conductive film 140 are electrically connected via the third conductive film 150.
    Type: Application
    Filed: September 7, 2016
    Publication date: September 6, 2018
    Inventors: TOHRU OKABE, HIROHIKO NISHIKI, TAKESHI HARA, TOMOHIRO KOSAKA, IZUMI ISHIDA, SHOGO MURASHIGE