Patents by Inventor Shogo Ogawa

Shogo Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145256
    Abstract: A method for manufacturing a semiconductor device includes preparing a plurality of semiconductor elements, preparing a support member, attaching the plurality of semiconductor elements to the support member so that second surfaces of the plurality of semiconductor elements face the support member, encapsulating the plurality of semiconductor elements with an encapsulation material, removing the support member from an encapsulation material layer in which the plurality of semiconductor elements is encapsulated with the encapsulation material, bonding a first protective film to a second surface of the encapsulation material layer located on the second surface side of the plurality of semiconductor elements, and forming a re-distribution layer on a first surface of the encapsulation material layer located on the first surface side of the plurality of semiconductor elements after bonding the first protective film to the encapsulation material layer.
    Type: Application
    Filed: March 4, 2022
    Publication date: May 2, 2024
    Inventors: Hiroaki MATSUBARA, Daisuke IKEDA, Shogo SOBUE, Saeko OGAWA
  • Patent number: 11931830
    Abstract: A control method for gas-shielded arc welding includes providing a normal arc period in which the welding current is maintained at a setting current Icc set in advance, and providing a separation control period after the separation timing of the molten droplet is detected in the normal arc period, the separation control period including a current decreasing section, a current maintaining section, and a current increasing section. In the separation control period, at least one of the following controls for preventing a short circuit is performed: control of an output voltage, control of a feeding speed, and control of a gas ratio.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 19, 2024
    Assignee: Kobe Steel, Ltd.
    Inventors: Baini Jo, Shogo Nakatsukasa, Akira Ogawa, Eiji Sato
  • Publication number: 20230058820
    Abstract: There is provided a semiconductor device including: an n-type semiconductor substrate having a first main surface and a second main surface on an opposite side of the first main surface; an n-type semiconductor layer arranged on the first main surface of the semiconductor substrate; a pair of trenches formed at a distance from each other on a surface of the semiconductor layer on an opposite side of the semiconductor substrate; a pair of gate electrodes buried in the pair of trenches; a gate insulating film interposed between the gate electrodes and the semiconductor layer; a source electrode formed on the surface of the semiconductor layer on the opposite side of the semiconductor substrate; and a drain electrode formed on the second main surface of the semiconductor substrate.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 23, 2023
    Inventor: Shogo OGAWA
  • Patent number: 10097174
    Abstract: A semiconductor device includes a switching element including a control electrode, a first main electrode, and a second main electrode: a gate driver connected between the control electrode and the first main electrode, configured to transmit a gate drive signal for driving the control electrode; a Miller voltage detector detecting a Miller voltage between the control electrode and the first main electrode when the switching element turns off; a current value detector detecting a principal current flowing through the switching element; and a temperature calculator calculating a temperature of the switching element from the detected Miller voltage and principal current.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 9, 2018
    Assignee: FUJI ELECTRONICS CO., LTD.
    Inventors: Shuangching Chen, Shogo Ogawa
  • Patent number: 10056175
    Abstract: In order to realize a thermistor on a base substrate without restricting the layout of a wiring layer, a thermistor mounting apparatus is provided, the thermistor mounting apparatus including a base substrate, and a thermistor component provided over the base substrate, in which the thermistor component has an insulating substrate, an electrode provided over the insulating substrate, and a thermistor provided over the insulating substrate and electrically connected to the electrode.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: August 21, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Sayaka Yamamoto, Shogo Ogawa
  • Patent number: 10056894
    Abstract: A drive unit of a semiconductor element including: a drive circuit for driving a control electrode of a voltage control semiconductor element to which a freewheeling diode is connected in anti-parallel; a resistor connected between the control electrode and the drive circuit; a capacitor having one terminal connected between the resistor and the control electrode; and a switch element connected between another terminal of the capacitor and a low-voltage-side electrode of the voltage control semiconductor element, wherein a control electrode of the switch element is connected to a connection point of the resistor and the capacitor.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 21, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuangching Chen, Shogo Ogawa
  • Patent number: 10003280
    Abstract: A semiconductor module, an upper and lower arm kit, and a three-level inverter can be provided at low cost and with broad current ratings and voltage ratings using existing packages, without developing new packages. A first semiconductor module on an upper arm side and a second semiconductor module on a lower arm side are made using an existing package, and the semiconductor modules and are used to configure an upper and lower arm kit. Further, the upper and lower arm kit is used to configure a three-level inverter. These devices can be formed using existing packages, and semiconductor modules, the upper and lower arm kit, and the three-level inverter can be therefore provided at low cost and with broad current ratings and voltage ratings.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: June 19, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shogo Ogawa
  • Publication number: 20180019744
    Abstract: A semiconductor device includes a switching element including a control electrode, a first main electrode, and a second main electrode: a gate driver connected between the control electrode and the first main electrode, configured to transmit a gate drive signal for driving the control electrode; a Miller voltage detector detecting a Miller voltage between the control electrode and the first main electrode when the switching element turns off; a current value detector detecting a principal current flowing through the switching element; and a temperature calculator calculating a temperature of the switching element from the detected Miller voltage and principal current.
    Type: Application
    Filed: May 22, 2017
    Publication date: January 18, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Shuangching CHEN, Shogo OGAWA
  • Publication number: 20170214336
    Abstract: A semiconductor module, an upper and lower arm kit, and a three-level inverter can be provided at low cost and with broad current ratings and voltage ratings using existing packages, without developing new packages. A first semiconductor module on an upper arm side and a second semiconductor module on a lower arm side are made using an existing package, and the semiconductor modules and are used to configure an upper and lower arm kit. Further, the upper and lower arm kit is used to configure a three-level inverter. These devices can be formed using existing packages, and semiconductor modules, the upper and lower arm kit, and the three-level inverter can be therefore provided at low cost and with broad current ratings and voltage ratings.
    Type: Application
    Filed: April 7, 2017
    Publication date: July 27, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shogo OGAWA
  • Publication number: 20170194954
    Abstract: A drive unit of a semiconductor element including: a drive circuit for driving a control electrode of a voltage control semiconductor element to which a freewheeling diode is connected in anti-parallel; a resistor connected between the control electrode and the drive circuit; a capacitor having one terminal connected between the resistor and the control electrode; and a switch element connected between another terminal of the capacitor and a low-voltage-side electrode of the voltage control semiconductor element, wherein a control electrode of the switch element is connected to a connection point of the resistor and the capacitor.
    Type: Application
    Filed: November 21, 2016
    Publication date: July 6, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Shuangching CHEN, Shogo OGAWA
  • Patent number: 9685888
    Abstract: A semiconductor module, an upper and lower arm kit, and a three-level inverter can be provided at low cost and with broad current ratings and voltage ratings using existing packages, without developing new packages. A first semiconductor module (100) on an upper arm side and a second semiconductor module (200) on a lower arm side are made using an existing package, and the semiconductor modules (100) and (200) are used to configure an upper and lower arm kit (300). Further, the upper and lower arm kit (300) is used to configure a three-level inverter (500). These devices can be formed using existing packages (56), and semiconductor modules (100), (200), the upper and lower arm kit (300), and the three-level inverter (500) can be therefore provided at low cost and with broad current ratings and voltage ratings.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: June 20, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shogo Ogawa
  • Publication number: 20160360620
    Abstract: In order to realize a thermistor on a base substrate without restricting the layout of a wiring layer, a thermistor mounting apparatus is provided, the thermistor mounting apparatus including a base substrate, and a thermistor component provided over the base substrate, in which the thermistor component has an insulating substrate, an electrode provided over the insulating substrate, and a thermistor provided over the insulating substrate and electrically connected to the electrode.
    Type: Application
    Filed: May 10, 2016
    Publication date: December 8, 2016
    Inventors: Sayaka YAMAMOTO, Shogo OGAWA
  • Patent number: 9178448
    Abstract: A power conversion device for driving a load, including a power conversion device main body configured to receive an input of a power supply voltage and to drive the load, and a brake circuit configured to protect the power conversion device main body from overvoltage applied thereto. The brake circuit includes a Zener diode that becomes conductive when the voltage applied to the power conversion device main body exceeds a predetermined value, to thereby suppress the voltage.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: November 3, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shogo Ogawa
  • Patent number: 9129960
    Abstract: A circuit assembly is disclosed which includes first and second substrates disposed on a heat dissipation base, and first and second semiconductor elements mounted on the first and second substrates. The first and second substrates are wired together, and three main electrode terminals are provided when the first and second semiconductor elements are connected in series, while two main electrode terminals are provided when the first and second semiconductor element are connected in parallel. In both cases, the circuit assembly is covered with a common exterior case so that one portion of each main electrode terminal or one portion of each main electrode terminal is exposed. Parts used in the circuit assembly are shared, and by changing the wiring between the first and second substrates, semiconductor modules with different functions are realized at low cost.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: September 8, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shogo Ogawa
  • Publication number: 20140231982
    Abstract: A circuit assembly is disclosed which includes first and second substrates disposed on a heat dissipation base, and first and second semiconductor elements mounted on the first and second substrates. The first and second substrates are wired together, and three main electrode terminals are provided when the first and second semiconductor elements are connected in series, while two main electrode terminals are provided when the first and second semiconductor element are connected in parallel. In both cases, the circuit assembly is covered with a common exterior case so that one portion of each main electrode terminal or one portion of each main electrode terminal is exposed. Parts used in the circuit assembly are shared, and by changing the wiring between the first and second substrates, semiconductor modules with different functions are realized at low cost.
    Type: Application
    Filed: March 20, 2014
    Publication date: August 21, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shogo OGAWA
  • Publication number: 20140203740
    Abstract: A power conversion device for driving a load, including a power conversion device main body configured to receive an input of a power supply voltage and to drive the load, and a brake circuit configured to protect the power conversion device main body from overvoltage applied thereto. The brake circuit includes a Zener diode that becomes conductive when the voltage applied to the power conversion device main body exceeds a predetermined value, to thereby suppress the voltage.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 24, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shogo OGAWA
  • Publication number: 20140169054
    Abstract: A semiconductor module, an upper and lower arm kit, and a three-level inverter can be provided with low cost and broad current ratings and voltage ratings using existing packages, without developing new packages. A first semiconductor module (100) on an upper arm side and a second semiconductor module (200) on a lower arm side are formed using an existing package, and the semiconductor modules (100) and (200) are used to configure an upper and lower arm kit (300). Further, the upper and lower arm kit (300) is used to configure a three-level inverter (500). These devices can be formed using existing packages (56), and semiconductor modules (100), (200), an upper and lower arm kit (300), and a three-level inverter (500) can be therefore provided with low cost and broad current ratings and voltage ratings.
    Type: Application
    Filed: June 6, 2012
    Publication date: June 19, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Shogo Ogawa
  • Patent number: 8542420
    Abstract: Certain embodiments provide an image reading apparatus including: a monochrome CCD sensor including a first photo-diode array; plural color CCD sensors each including a second photodiode array; an AD converter configured to apply analog-to-digital conversion to each of analog outputs from the second photodiode array and the first photodiode array; a delay processing unit configured to delay at least one of color image data of plural colors from the AD converter and interpolate, with delayed any one or more of the color image data, a blank of image data that is to be read on a line in a sub-scanning direction; and an inter-line correction unit configured to correct, by the intervals and a set reduction magnification, a positional deviation in the sub-scanning direction between the monochrome image data and the color image data, respective timings of which are aligned on the line by the delay processing unit.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: September 24, 2013
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventors: Shogo Ogawa, Yoshio Yoshimura, Tadashi Mokudai
  • Publication number: 20120002254
    Abstract: Certain embodiments provide an image reading apparatus including: a monochrome CCD sensor including a first photo-diode array; plural color CCD sensors each including a second photodiode array; an AD converter configured to apply analog-to-digital conversion to each of analog outputs from the second photodiode array and the first photodiode array; a delay processing unit configured to delay at least one of color image data of plural colors from the AD converter and interpolate, with delayed any one or more of the color image data, a blank of image data that is to be read on a line in a sub-scanning direction; and an inter-line correction unit configured to correct, by the intervals and a set reduction magnification, a positional deviation in the sub-scanning direction between the monochrome image data and the color image data, respective timings of which are aligned on the line by the delay processing unit.
    Type: Application
    Filed: June 27, 2011
    Publication date: January 5, 2012
    Applicants: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha Toshiba
    Inventors: Shogo Ogawa, Yoshio Yoshimura, Tadashi Mokudai
  • Patent number: 5599864
    Abstract: A polyarylene sulfide resin composition having an excellent fluidability and a good moldability is disclosed. The resin composition is useful as a material for an optical pick-up part which has a high reliability and a high tenacity and does not generate deviation of an optical axis with changes in environmental conditions such as temperature and humidity. The polyarylene sulfide resin composition comprises, as main components, a polyarylene sulfide resin, a fibrous filler and a particulate filler, and, optionally, a silane coupling agent and an alicyclic hydrocarbon.
    Type: Grant
    Filed: October 3, 1994
    Date of Patent: February 4, 1997
    Assignees: Kabushiki Kaisha Sankyo Seiki Seisakusho, Shikoku Chemicals Corporation
    Inventors: Shogo Ogawa, Hajime Hata, Ikuo Kasuga, Hiromasa Marumo, Masamichi Hayakawa