Patents by Inventor Shohei Asami

Shohei Asami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210110875
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
  • Patent number: 10964712
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
  • Patent number: 10908659
    Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuka Kuwano, Takehiko Amaki, Toshikatsu Hida, Shohei Asami
  • Patent number: 10910067
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Shohei Asami, Masamichi Fujiwara
  • Patent number: 10777283
    Abstract: A memory system includes a semiconductor memory including memory cells and a memory controller configured to perform a first tracking process to determine a first voltage, and to read data using the first voltage in a read process after the first tracking process. In the first tracking process, the memory controller is configured to read only first, second, and third data respectively using a second, third, and fourth voltage, determine a number of first memory cells based on the first and second data, determine a number of second memory cells based on the second and third data, and determine the first voltage, based on the number of first and second memory cells.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: September 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shohei Asami, Toshikatsu Hida
  • Patent number: 10770147
    Abstract: A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Asami, Toshikatsu Hida
  • Patent number: 10719396
    Abstract: A controller executes a plurality of first read operations and, when receiving a read request from a host, executes a second read operation. The first read operations are executed using, as determination voltage, different candidate values among a plurality of candidate values. In each of the first read operations, the controller executes error correction to acquired data, and acquires a first candidate value on the basis of results of the error corrections in the first read operations. The second read operation is executed using, as the determination voltage, a second candidate value that is ranked higher than the first candidate value.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shohei Asami, Yoshihisa Kojima
  • Publication number: 20200211654
    Abstract: A memory system includes a semiconductor memory including memory cells and a memory controller configured to perform a first tracking process to determine a first voltage, and to read data using the first voltage in a read process after the first tracking process. In the first tracking process, the memory controller is configured to read only first, second, and third data respectively using a second, third, and fourth voltage, determine a number of first memory cells based on the first and second data, determine a number of second memory cells based on the second and third data, and determine the first voltage, based on the number of first and second memory cells.
    Type: Application
    Filed: September 10, 2019
    Publication date: July 2, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Shohei Asami, Toshikatsu Hida
  • Publication number: 20200083240
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Takehiko AMAKI, Yoshihisa KOJIMA, Toshikatsu HIDA, Marie Grace Izabelle Ange SIA, Riki SUZUKI, Shohei ASAMI
  • Publication number: 20200075106
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.
    Type: Application
    Filed: March 11, 2019
    Publication date: March 5, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
  • Patent number: 10529730
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: January 7, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
  • Publication number: 20190286518
    Abstract: A controller executes a plurality of first read operations and, when receiving a read request from a host, executes a second read operation. The first read operations are executed using, as determination voltage, different candidate values among a plurality of candidate values. In each of the first read operations, the controller executes error correction to acquired data, and acquires a first candidate value on the basis of results of the error corrections in the first read operations. The second read operation is executed using, as the determination voltage, a second candidate value that is ranked higher than the first candidate value.
    Type: Application
    Filed: February 6, 2019
    Publication date: September 19, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Shohei ASAMI, Yoshihisa KOJIMA
  • Publication number: 20190094927
    Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.
    Type: Application
    Filed: June 18, 2018
    Publication date: March 28, 2019
    Inventors: Yuka KUWANO, Takehiko AMAKI, Toshikatsu HIDA, Shohei ASAMI
  • Publication number: 20190074283
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Application
    Filed: August 1, 2018
    Publication date: March 7, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Takehiko AMAKI, Yoshihisa Kojima, Toshikatsu Hida, Marie Sia, Riki Suzuki, Shohei Asami
  • Publication number: 20180091170
    Abstract: A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 29, 2018
    Inventors: Shohei ASAMI, Toshikatsu HIDA
  • Patent number: 9891848
    Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Asami, Tokumasa Hara, Hiroshi Yao, Kenichiro Yoshii, Riki Suzuki, Toshikatsu Hida, Osamu Torii
  • Patent number: 9875803
    Abstract: According to one embodiment, a controller searches a threshold voltage distribution of first memory cells corresponding to a first processing unit that is one processing unit among a plurality of processing units, and acquires a first read voltage. The controller calculates a second read voltage that is a read voltage for second memory cells corresponding to a second processing unit based on the acquired first read voltage and a first relation. The controller reads data from third memory cells included in the second memory cells by using the calculated second read voltage.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: January 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shohei Asami, Toshikatsu Hida
  • Publication number: 20170076807
    Abstract: According to one embodiment, a controller searches a threshold voltage distribution of first memory cells corresponding to a first processing unit that is one processing unit among a plurality of processing units, and acquires a first read voltage. The controller calculates a second read voltage that is a read voltage for second memory cells corresponding to a second processing unit based on the acquired first read voltage and a first relation. The controller ads data from third memory cells included in the second memory cells by using the calculated second read voltage.
    Type: Application
    Filed: March 9, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shohei ASAMI, Toshikatsu Hida
  • Patent number: 9568987
    Abstract: According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory, and a controller which is configured to turn off a power of the volatile memory after storing data of the volatile memory in the nonvolatile memory in a first mode, turn on the power of the volatile memory in the second mode, and change a first timing as a future timing switching to the first mode based on a second timing as a past timing switching to the second mode.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: February 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuru Anazawa, Toshikatsu Hida, Shohei Asami
  • Patent number: 9564930
    Abstract: According to one embodiment, a memory controller includes an encoding unit that generates a first code word, a duplication unit that duplicates the first code word, a memory interface that writes a code word group including the first code word and code words being duplicates of the first code word into a non-volatile memory, and reads the code words forming the code word group from the non-volatile memory, a determination unit that obtains a result of majority decision using the first code word and the plurality of code words, which are included in the code word group read from the non-volatile memory, and a decoding unit that decodes a code word being the result of the majority decision and corrects an error.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 7, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Riki Suzuki, Toshikatsu Hida, Mitsunori Tadokoro, Yoshihisa Kojima, Shohei Asami