Patents by Inventor Shohei Asami
Shohei Asami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11348934Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: GrantFiled: February 23, 2021Date of Patent: May 31, 2022Assignee: Kioxia CorporationInventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
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Publication number: 20220130468Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.Type: ApplicationFiled: January 4, 2022Publication date: April 28, 2022Applicant: Kioxia CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
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Patent number: 11309051Abstract: According to one embodiment, a memory system includes: a memory chip including a first memory block and first word lines, the first memory block including a first memory string which includes first memory cells that are coupled in series, the first word lines being respectively coupled to gates of the first memory cells; a memory controller coupled to an external device, controlling the memory chip, and capable of performing an error checking and correcting process of data. When a write instruction is received from the external device, the memory controller is configured to perform a write operation on a second memory cell which is one of the first memory cells, and to perform a read verify operation including a read process and the ECC process on a third memory cell which is one of the first memory cells.Type: GrantFiled: September 16, 2020Date of Patent: April 19, 2022Assignee: Kioxia CorporationInventors: Shohei Asami, Takehiko Amaki
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Publication number: 20220093169Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.Type: ApplicationFiled: June 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Shohei ASAMI, Toshikatsu HIDA, Riki SUZUKI
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Patent number: 11222703Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.Type: GrantFiled: December 22, 2020Date of Patent: January 11, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Shohei Asami, Masamichi Fujiwara
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Publication number: 20210295941Abstract: According to one embodiment, a memory system includes: a memory chip including a first memory block and first word lines, the first memory block including a first memory string which includes first memory cells that are coupled in series, the first word lines being respectively coupled to gates of the first memory cells; a memory controller coupled to an external device, controlling the memory chip, and capable of performing an error checking and correcting process of data. When a write instruction is received from the external device, the memory controller is configured to perform a write operation on a second memory cell which is one of the first memory cells, and to perform a read verify operation including a read process and the ECC process on a third memory cell which is one of the first memory cells.Type: ApplicationFiled: September 16, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Shohei ASAMI, Takehiko AMAKI
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Publication number: 20210183877Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: ApplicationFiled: February 23, 2021Publication date: June 17, 2021Applicant: Toshiba Memory CorporationInventors: Takehiko AMAKI, Yoshihisa KOJIMA, Toshikatsu HIDA, Marie Grace Izabelle Angeles SIA, Riki SUZUKI, Shohei ASAMI
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Publication number: 20210110875Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
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Patent number: 10964712Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: GrantFiled: November 14, 2019Date of Patent: March 30, 2021Assignee: Toshiba Memory CorporationInventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
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Patent number: 10908659Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.Type: GrantFiled: June 18, 2018Date of Patent: February 2, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuka Kuwano, Takehiko Amaki, Toshikatsu Hida, Shohei Asami
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Patent number: 10910067Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.Type: GrantFiled: March 11, 2019Date of Patent: February 2, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada, Shohei Asami, Masamichi Fujiwara
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Patent number: 10777283Abstract: A memory system includes a semiconductor memory including memory cells and a memory controller configured to perform a first tracking process to determine a first voltage, and to read data using the first voltage in a read process after the first tracking process. In the first tracking process, the memory controller is configured to read only first, second, and third data respectively using a second, third, and fourth voltage, determine a number of first memory cells based on the first and second data, determine a number of second memory cells based on the second and third data, and determine the first voltage, based on the number of first and second memory cells.Type: GrantFiled: September 10, 2019Date of Patent: September 15, 2020Assignee: Toshiba Memory CorporationInventors: Shohei Asami, Toshikatsu Hida
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Patent number: 10770147Abstract: A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.Type: GrantFiled: March 1, 2017Date of Patent: September 8, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shohei Asami, Toshikatsu Hida
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Patent number: 10719396Abstract: A controller executes a plurality of first read operations and, when receiving a read request from a host, executes a second read operation. The first read operations are executed using, as determination voltage, different candidate values among a plurality of candidate values. In each of the first read operations, the controller executes error correction to acquired data, and acquires a first candidate value on the basis of results of the error corrections in the first read operations. The second read operation is executed using, as the determination voltage, a second candidate value that is ranked higher than the first candidate value.Type: GrantFiled: February 6, 2019Date of Patent: July 21, 2020Assignee: Toshiba Memory CorporationInventors: Shohei Asami, Yoshihisa Kojima
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Publication number: 20200211654Abstract: A memory system includes a semiconductor memory including memory cells and a memory controller configured to perform a first tracking process to determine a first voltage, and to read data using the first voltage in a read process after the first tracking process. In the first tracking process, the memory controller is configured to read only first, second, and third data respectively using a second, third, and fourth voltage, determine a number of first memory cells based on the first and second data, determine a number of second memory cells based on the second and third data, and determine the first voltage, based on the number of first and second memory cells.Type: ApplicationFiled: September 10, 2019Publication date: July 2, 2020Applicant: Toshiba Memory CorporationInventors: Shohei Asami, Toshikatsu Hida
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Publication number: 20200083240Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Applicant: Toshiba Memory CorporationInventors: Takehiko AMAKI, Yoshihisa KOJIMA, Toshikatsu HIDA, Marie Grace Izabelle Ange SIA, Riki SUZUKI, Shohei ASAMI
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Publication number: 20200075106Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.Type: ApplicationFiled: March 11, 2019Publication date: March 5, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Marie TAKADA, Shohei ASAMI, Masamichi FUJIWARA
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Patent number: 10529730Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.Type: GrantFiled: August 1, 2018Date of Patent: January 7, 2020Assignee: Toshiba Memory CorporationInventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
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Publication number: 20190286518Abstract: A controller executes a plurality of first read operations and, when receiving a read request from a host, executes a second read operation. The first read operations are executed using, as determination voltage, different candidate values among a plurality of candidate values. In each of the first read operations, the controller executes error correction to acquired data, and acquires a first candidate value on the basis of results of the error corrections in the first read operations. The second read operation is executed using, as the determination voltage, a second candidate value that is ranked higher than the first candidate value.Type: ApplicationFiled: February 6, 2019Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Shohei ASAMI, Yoshihisa KOJIMA
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Publication number: 20190094927Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.Type: ApplicationFiled: June 18, 2018Publication date: March 28, 2019Inventors: Yuka KUWANO, Takehiko AMAKI, Toshikatsu HIDA, Shohei ASAMI