Abstract: Parallel inductors include a first metal wire (8a or 8b) for connecting a drain terminal (2) and a first metal pattern (7a or 7b), and a second metal wire (10a or 10b) for connecting the first metal pattern (7a or 7b) and a second metal pattern (9a or 9b). The second metal wires (10a and 10b) are each positioned between the corresponding first metal wire (8a or 8b) and a corresponding third metal wire (12a or 12b) for connecting the drain terminal (2) and a third metal pattern (11). The direction of current through the second metal wires (10a and 10b) is opposite to the direction of current through each of the first metal wire (8a or 8b) and the third metal wire (12a or 12b).

Abstract: A multi-finger transistor includes a circuit suppressing a variation in voltage current distribution. The circuit connects gate fingers (21) to each other, or source fingers (31) to each other in a region which is located outside an active region (11) and on a side where a drain pad (42) is disposed. The multi-finger transistor is configured to be linearly symmetric with respect to a direction of propagation of a signal from a gate pad (22) at the position of the gate pad (22).

Abstract: A semiconductor device includes: a depletion-type field-effect transistor including a gate terminal, a drain terminal and a source terminal; a group III-V heterojunction bipolar transistor including a base terminal, an emitter terminal electrically connected to the gate terminal and a collector terminal connected to same potential as that of the source terminal; a first resistor connected between the base terminal and the emitter terminal; and a second resistor connected between the base terminal and the collector terminal.

Abstract: A semiconductor device is provided with one or more gate fingers (20) that are provided in an active region on a semiconductor substrate (1), and a source finger (30) and a drain finger (40) that are provided in the active region and arranged alternately to allow each gate finger to be sandwiched between the source and drain fingers. The semiconductor device includes terminal circuit (60) that has inductive impedance at the frequency of a signal input to an input terminal of the one or more gate fingers, and is directly or indirectly connected to the one or more gate fingers at an area being spaced away from a connecting position of the input terminal (21a) of the one or more gate fingers (20).

Abstract: A multi-finger transistor includes a circuit suppressing a variation in voltage current distribution. The circuit connects gate fingers (21) to each other, or source fingers (31) to each other in a region which is located outside an active region (11) and on a side where a drain pad (42) is disposed. The multi-finger transistor is configured to be linearly symmetric with respect to a direction of propagation of a signal from a gate pad (22) at the position of the gate pad (22).

Abstract: A semiconductor device includes: a depletion-type field-effect transistor including a gate terminal, a drain terminal and a source terminal; a group III-V heterojunction bipolar transistor including a base terminal, an emitter terminal electrically connected to the gate terminal and a collector terminal connected to same potential as that of the source terminal; a first resistor connected between the base terminal and the emitter terminal; and a second resistor connected between the base terminal and the collector terminal.

Abstract: An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.

Abstract: A configuration is provided with: a tuned line 13 that is connected between a branch terminal 3 and a branch terminal of branch lines 2 and 4; and a tuned line 14 that is connected between a combining terminal 7 and a combining terminal 9 of combining lines 10 and 11. This enables reduction of a non-uniform voltage distribution occurring due to a difference in characteristics between two amplifier elements 6 and 8.

Abstract: An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.

Abstract: A high frequency device includes a base plate having a main surface, a dielectric on the main surface, along a first side of the base plate, a signal line on the dielectric and extending from the first side toward a central portion of the main surface, an island pattern of a metal on the dielectric, a metal frame having a contact portion contacting the main surface and a bridge portion on the signal line and the island pattern, together enclosing the central portion, a lead frame connected to an outside signal line of the signal line and which is located outside the metal frame, a semiconductor chip secured to the central portion, and a wire connecting the semiconductor chip to an inside signal line of the signal line and which is enclosed within the metal frame.

Abstract: A configuration is provided with: a tuned line 13 that is connected between a branch terminal 3 and a branch terminal of branch lines 2 and 4; and a tuned line 14 that is connected between a combining terminal 7 and a combining terminal 9 of combining lines 10 and 11. This enables reduction of a non-uniform voltage distribution occurring due to a difference in characteristics between two amplifier elements 6 and 8.

Abstract: A high frequency device includes a base plate having a main surface, a dielectric on the main surface, along a first side of the base plate, a signal line on the dielectric and extending from the first side toward a central portion of the main surface, an island pattern of a metal on the dielectric, a metal frame having a contact portion contacting the main surface and a bridge portion on the signal line and the island pattern, together enclosing the central portion, a lead frame connected to an outside signal line of the signal line and which is located outside the metal frame, a semiconductor chip secured to the central portion, and a wire connecting the semiconductor chip to an inside signal line of the signal line and which is enclosed within the metal frame.