Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

Abstract: An AlCu alloy interconnect line (100) including a TiN barrier layer (110), a lower Ti metal layer (120), an AlCu layer (130) and a TiN cap layer (140) is formed on a plasma oxide film formed on a semiconductor substrate in which devices are formed. Heat treatment is conducted to cause Al contained in the AlCu layer (130) and Ti contained in the lower Ti metal layer (120) to react with each other, thereby forming a lower AlTi alloy layer (150) in a lower portion of the AlCu layer (130). A via hole (170) is thereafter formed. A current path extending from the via hole (170) to reach the lower AlTi alloy layer (150) is ensured without passing through the AlCu layer (130), allowing electromigration resistance to be improved.

Abstract: A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via source/drain regions 14b and 16a, is defined in the lower interlayer insulating film 20. A local wiring 24 is buried in the through hole 22 to connect each gate electrode 14c and the source/drain regions 14b and 16a. Further, an upper interlayer insulating film 26 is provided on the local wiring 24 and the lower interlayer insulating film 20. Upper electrode layers 28 are placed on the surface of the upper interlayer insulating film 26.

Abstract: A semiconductor-device fabrication method includes a step of forming a contact hole in a semiconductor substrate 1 and a step of forming a conductive contact hole. The step of forming the contact hole is performed by repeating two times or more a burying step of depositing a conductive material 5 to bury the conductive material in the contact hole and an etch-back step of removing the conductive material around the contact hole by etch back.

Abstract: It is an object to enhance an adhesion strength of a bonding pad in a semiconductor device having a fluorine doped silicon oxide film as an interlayer insulating film. A second interlayer insulating film (4) provided with a bonding pad (6) on an upper surface has a three-layered structure including an F doped silicon oxide film (4a), a TEOS based silicon oxide film (4b) and an SiH4 based silicon oxide film (4c). A dummy pattern (10) having an equal size to that of the bonding pad (6) is provided in a region right under the bonding pad (6), and the F doped silicon oxide film (4a) and the SiH4 based silicon oxide film (4c) are in contact with each other in a region right on the dummy pattern (10). More specifically, an interface of the TEOS based silicon oxide film (4b) and the SiH4 based silicon oxide film (4c) is hardly present in a region right under the bonding pad (6).

Abstract: A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via source/drain regions 14b and 16a, is defined in the lower interlayer insulating film 20. A local wiring 24 is buried in the through hole 22 to connect each gate electrode 14c and the source/drain regions 14b and 16a. Further, an upper interlayer insulating film 26 is provided on the local wiring 24 and the lower interlayer insulating film 20. Upper electrode layers 28 are placed on the surface of the upper interlayer insulating film 26.

Abstract: A semiconductor-device fabrication method includes a step of forming a contact hole in a semiconductor substrate 1 and a step of forming a conductive contact hole. The step of forming the contact hole is performed by repeating two times or more a burying step of depositing a conductive material 5 to bury the conductive material in the contact hole and an etch-back step of removing the conductive material around the contact hole by etch back.

Abstract: A vibration wave detector having a first diaphragm for receiving vibration waves, such as sound waves and so on, to be propagated in a medium, a resonant unit having a plurality of cantilever resonators each having such a length as to resonate at an individual predetermined frequency, a retaining rod for retaining the resonant unit, a second diaphragm positioned on the opposite side of the first diaphragm with respect to the retaining rod, and a vibration intensity detector for detecting the vibration intensity, for each predetermined frequency, of each of the resonators, by the vibration waves received by the first diaphragm and propagated to the resonant unit through the retaining rod.