Patents by Inventor Shoichi Iriguchi

Shoichi Iriguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200027772
    Abstract: A die matrix expander includes a subring including ?3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter <an inner diameter of the wafer frame. A translation guide coupled to the subring driven by mechanical force applier moves the subring pieces in an angled path upwards and outwards for stretching the dicing tape including to a top most stretched position above the wafer frame that is over or outside the wafer frame. A cap placed on the pieces of the subring after being fully expanded over the dicing tape locks the dicing tape in the top most stretched position and secures the pieces of the expanded subring in place including when within the indentation during an additional expansion during a subsequent die pick operation.
    Type: Application
    Filed: July 23, 2018
    Publication date: January 23, 2020
    Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, DAVE CHARLES STEPNIAK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO
  • Publication number: 20190330596
    Abstract: A method for producing CD4/CD8 double-positive T cells, comprising the steps of: (1) culturing pluripotent stem cells in a medium to induce hematopoietic progenitor cells; and (2) culturing the hematopoietic progenitor cells obtained in the step (1) in a medium containing a p38 inhibitor and/or SDF-1 to induce CD4/CD8 double-positive T cells.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 31, 2019
    Applicant: Kyoto University
    Inventors: Shin KANEKO, Yutaka YASUI, Shoichi IRIGUCHI, Tatsuki UEDA
  • Publication number: 20170338184
    Abstract: A method of dicing an integrated circuit wafer by partially sawing the scribe street from the backside of the wafer and then completing sawing the scribe street from the front side of the wafer. A method of dicing an integrated circuit wafer by backgrinding the wafer prior to partially sawing the scribe street from the backside of the wafer and then completing sawing the scribe street from the front side of the wafer.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 23, 2017
    Inventor: Shoichi Iriguchi
  • Patent number: 8993412
    Abstract: In one aspect of the present invention, a method of sawing a semiconductor wafer will be described. A semiconductor wafer is positioned in a wafer sawing apparatus that includes a sawing blade and a movable support structure that physically supports the semiconductor wafer. The semiconductor wafer is coupled with the support structure with various layers, including a dicing tape and an anchoring material. The anchoring material and the wafer are cut with the sawing blade. During the cutting operation, the anchoring material reduces backside chipping of the die and eliminates fly-away die. Various aspects of the present invention relate to arrangements and a wafer sawing apparatus that involve the aforementioned sawing method.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: March 31, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Shoichi Iriguchi, Noboru Nakanishi