Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOGOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.

Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.

Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.

Abstract: A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of opposite conductivity type. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers, which are in separated patterns.

Abstract: In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.

Abstract: In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.

Abstract: A semiconductor device including an input protective circuit. A first transistor has a gate formed on the semiconductor substrate and a first and second conductive region is formed on each side of the first gate. Third and fourth conductive regions are respectively formed between the first and second conductive regions and the gate. The third conductive region has a resistance higher than that of the first conductive region, and the fourth conductive region has a conductivity type opposite to the conductivity type of the remaining regions. A second transistor is formed with a pair of conductive regions at an insulated gate. One of the pair of conductive regions is of the second transistor connected to the first transistor, first or second conductive region.

Abstract: In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.

Abstract: A polycide wiring layer constituted by a polysilicon film and a silicide film is used as a bit line of a DRAM. When a memory cell region having an n-type impurity diffusion layer and a peripheral circuit region having a p-type impurity diffusion layer are to be electrically connected through the polysilicon film, a diffusion prevention film consisting of TiSiN or WSiN is formed as an underlying film of the polysilicon film. With this diffusion prevention film, interdiffusion between the n- and p-type impurity diffusion layers can be prevented. In addition, heat resistance at 900.degree. C. or more can be obtained in processes after formation of the diffusion prevention film.

Abstract: A semiconductor memory device has word line conductor films, bit line conductor films transverse to the word line conductor films and memory cells provided at intersections between the word line conductor films and bit line conductor films. Each memory cell has a transistor structure formed at a surface portion of a semiconductor substrate and a capacitor structure formed over the semiconductor substrate. The word line conductor films are formed at a level lower than the capacitor structures of the memory cells to improve the resolution of patterns for the semiconductor memory device.

Abstract: The semiconductor memory device comprises a field shield element isolation structure for defining a plurality of element regions electrically isolated from one another; a plurality of memory cells disposed in a matrix of rows and columns, each including a transistor having two impurity diffusion layers, a gate electrode and a capacitor; a plurality of bit lines extending in a row direction; a plurality of word lines extending in a column direction; a plurality of memory cell pairs, each formed in one of the element regions and including adjacent two of the memory cells disposed in the row direction, wherein each of the transistors of the two memory cells in each memory cell pair has two impurity diffusion layers, one of which is common to both the transistors and connected to one of the bit lines extending in the row direction immediately thereabove through a first pad polycrystalline silicon film; a second pad polycrystalline silicon film formed on the other impurity diffusion layer of each transistor so as

Abstract: A semiconductor memory device has word line conductor films, bit line conductor films transverse to the word line conductor films and memory cells provided at intersections between the word line conductor films and bit line conductor films. Each memory cell has a transistor structure formed at a surface portion of a semiconductor substrate and a capacitor structure formed over the semiconductor substrate. The word line conductor films are formed at a level lower than the capacitor structures of the memory cells to improve the resolution of patterns for the semiconductor memory device.

Abstract: A semiconductor device has a memory cell array and a filtering capacitor for suppressing noise in a power supply voltage to the device, both formed with one and the same semiconductor substrate. The memory cell array includes memory cells each having a transfer transistor and an information storage capacitor. The transistor of each memory cell has a pair of source/drain regions formed in an active region defined by first isolation regions in a main surface of the semiconductor substrate. Lead electrodes are formed on the source/drain regions. The information storage capacitor of each cell has a lower electrode formed in an electrical connection with a first one of the pair of source/drain regions, a dielectric film and an upper electrode formed on the dielectric film. The filtering capacitor is formed on a second isolation region also formed at the main surface of the semiconductor substrate and has a dielectric layer including an oxide film and a nitride film.

Abstract: A semiconductor substrate has two element forming regions and one element separation region between the two element forming regions. A shield electrode for electrically separating the two element forming regions is formed in the semiconductor substrate at the element separating region. A trench capacitor is formed in the semiconductor substrate at the element separation region. The trench capacitor has a trench, a first conductive layer covering at least the inner wall of the trench, a dielectric layer formed at least on the first conductive layer in the trench, and a second conductive layer formed at least on the dielectric layer in the trench. The shield electrode and the first conductive layer is made of the same layer. A transistor having a pair of impurity doped regions is formed in the semiconductor substrate at the element forming region, the second conductive layer of the trench capacitor is electrically connected to one of the pair of impurity doped regions of the transistor.

Abstract: A semiconductor memory device comprises a plurality of memory cells on a semiconductor substrate, each including a transistor with a pair of impurity diffusion layers and a gate electrode, and a capacitor, a first insulating film covering the transistors, a plurality of parallel extending word lines formed on the substrate, each being connected to the gate electrode of the transistor of at least one selected memory cell, a plurality of bit lines, each connected to one of the pair of impurity diffusion layers of at least one selected memory cell through a first contact hole in the first insulating layer, each bit line formed with a conductive film on a top surface thereof and a second insulating film interposed therebetween, a lower electrode of the capacitor at a predetermined position on the first insulating film electrically connected to one of the bit lines and to the other of the pair of impurity diffusion layers through a second contact hole formed in the first insulating film, wherein the conductive fil

Abstract: A semiconductor memory device comprises a field shield element isolation structure defining a plurality of electrically isolated element regions and a plurality of memory cells in a matrix of rows and columns, each including a transistor having two impurity diffusion layers, a gate electrode and a capacitor. A plurality of bit lines extends in a row direction and a plurality of word lines in a column direction. A memory cell pair is formed in each of the element regions and includes two adjacent memory cells disposed in the row direction. Each of the transistors of the two memory cells in each pair has two impurity diffusion layers, one of which is common to both transistors and connected to one of the bit lines extending in the row direction immediately thereabove through a first pad polycrystalline silicon film. A second pad is formed on the other impurity diffusion layer of each transistor to extend over a portion of the element isolation structure and adjacent thereto in the column direction.

Abstract: For manufacturing an insulated-gate field-effect transistor in a semiconductor device, a refractory metal film is formed over a semiconductor substrate with an insulating film being interposed therebetween. An insulated gate electrode is formed by patterning the refractory metal film and insulating film. After formation of source/drain regions in a surface portion of the substrate, using the insulated gate electrode as a mask, a poly-silicon film is formed extending to cover the surface portion of the substrate and the patterned refractory metal film of the gate electrode. The resulting structure is heated to convert at least that portion of the poly-silicon film which lies on the patterned refractory metal film to a silicide film portion. The thus formed silicide film portion is removed so that portions of the doped poly-silicon film are left on the source/drain regions in the surface portion of semiconductor substrate. These left portions of the doped poly-silicon film serve as source/drain electrodes.

Abstract: A pair of electrically conductive regions of ruthenium dioxide are formed on a BPSG film covering DRAM memory cells arranged in a matrix form. The conductive region is extended in a column direction to be connected to one of impurity diffused regions of MOS transistors of the memory cells at contact holes, and also connected to one of impurity diffused regions of MOS transistors of column direction selection. Formed beneath the conductive region (capacitor upper electrodes) are capacitor lower electrodes connected to the other impurity diffused regions of the memory cell MOS transistors and a high-dielectric film. The conductive region is connected to a (1/2)Vcc power supply. Since the upper electrodes and wiring lines of capacitors can be formed at the same time, the number of steps in a fabrication method can be reduced.

Abstract: An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

Abstract: In a semiconductor memory device and a method for using the semiconductor memory device, the semiconductor memory device includes a plurality of memory cells series-connected to each other, and each formed by a P-channel transistor in which a control gate electrode is stacked via an insulating film on a floating gate electrode. One end of the plural memory cells series-connected to each other is connected to one of a source and a drain of a first selecting transistor. The other of the source and the drain of the first selecting transistor are connected to a bit line. The other end of the plural memory cells series-connected to each other is connected to one of a source and a drain of a second selecting transistor. The other of the source and the drain of the second selecting transistor is connected to a power source line.