Abstract: For manufacturing an insulated-gate field-effect transistor in a semiconductor device, a refractory metal film is formed on a semiconductor substrate with an insulating film being interposed therebetween. An insulated gate electrode is formed by patterning the refractory metal film and insulating film. After formation of source/drain regions in a surface of the substrate, using the insulated gate electrode as a mask, a poly-silicon film is formed to cover the surface portion of the substrate and the patterned refractory metal film of the gate electrode. The resulting structure is heated to convert at least that portion of the poly-silicon film which lies on the patterned refractory metal film to a silicide film portion. The thus formed silicide film portion is removed so that portions of the doped poly-silicon film are left on the source/drain regions in the surface of semiconductor substrate. These portions of the doped poly-silicon film serve as source/drain electrodes.

Abstract: A nonvolatile semiconductor memory device comprises: a semiconductor substrate; a pair of spaced electrode films formed on a surface of the semiconductor substrate and having respective side faces opposing each other with a gap formed between them; a pair of diffusion layers formed in the surface of the semiconductor substrate and having respective end portions aligned with the side faces of the electrode films; an insulating film covering the gap and the spaced electrode films; a gate electrode formed on the insulating film to cover the gap and to extend above the pair of electrode films; and wiring layers directly connected to the pair of electrode films, respectively.

Abstract: A non-volatile semiconductor memory device comprises a plurality of semiconductor layers of a first conductivity type, extending parallelly in a column direction and isolated from each other; a plurality of memory cells disposed in a matrix of columns and rows, each having source and drain regions of a second conductivity type, a channel region between the source and drain regions and a gate structure formed on the channel region with a gate insulating layer interposed therebetween and including a floating gate, an interlayer insulating layer, and a control gate. The memory cells are divided into a plurality of groups formed on the semiconductor layers, respectively, so that all the memory cell groups are formed on one of the semiconductor layers and the drain-source circuits of the memory cells of each group are connected to form a series electrical path.

Abstract: A MOS semiconductor device and a method of making the same are arranged to include a semiconductor substrate of a first conductivity type; a pair of impurity diffused layers of a second conductivity type different from the first conductivity type formed in the semiconductor substrate and mutually separated by a distance of 0.1 .mu.m or less; a gate insulating film including at least two layers of a silicon oxide film and a silicon nitride film and formed on a portion of the semiconductor substrate disposed between the pair of impurity diffused layers; and a gate electrode formed on the gate insulating film, wherein preferably the silicon nitride film has a thickness of 4.5 nm to 14.86 nm.

Abstract: A non-volatile semiconductor memory device capable of selectively storing one of at least three different data comprises a memory array including a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source, a circuit for producing a stepped voltage whose level is varied stepwise to a number of different levels corresponding to a number of data to be stored, a circuit for producing a pulse voltage having a predetermined voltage level and a predetermined pulse width, and a circuit for selecting one of the plurality of memory cells, wherein during storing of the at least three different data the stepped voltage and the pulse voltage are applied to the control gate and the drain of the selected memory cell, respectively, while a timing of application of the pulse voltage to the drain is controlled relative to a timing of application of the stepped voltage to the control gate, depending on which of the at least three different data is to be stored into the selected memory cell.

Abstract: A method of using a non-volatile semiconductor memory comprising a plurality of row and column lines, a plurality of memory cells disposed at intersections of the row and column lines and a plurality of reference cells disposed on each of the row lines. Each memory cell includes an MOS transistor having a substrate, a spaced-apart drain and source formed on one surface of the substrate, a channel region between the drain and source and a lamination of a tunnel insulating film, a floating gate, an interlayer insulating film and a control gate formed in that order on the channel region.

Abstract: A semiconductor integrated circuit device comprising a temperature sensor including an element having a PN junction, an inverter for receiving an output of the temperature sensor, and a controller for controlling supply of an electric energy to a group of MOS integrated circuit elements on the basis of an output of the inverter, wherein the supply of the electric energy to the group of MOS integrated circuit elements is controlled on the basis of the output of the temperature sensor to automatically prevent the breakdown of the internal circuit due to excessive temperature rise by the device itself.

Abstract: The MOS field-effect transistor has a semiconductor substrate of a first conductivity type, a pair of first polycrystalline silicon layers of a second conductivity type different from the first conductivity type which are formed on the semiconductor substrate and separated from each other by a small gap, a pair of diffusion layers of the second conductivity type formed in those regions of the semiconductor substrate which are in contact with the pair of first polycrystalline silicon layers, respectively, a gate insulating film formed to cover the pair of first polycrystalline silicon layers of the second conductivity type and a part of the semiconductor substrate exposed to an outside at the small gap, and a gate electrode formed on the gate insulating film. The nonvolatile semiconductor memory device is arranged by using the MOS field-effect transistor mentioned above.

Abstract: A MOS semiconductor memory device comprises a semiconductor substrate of a first conductive type; impurity diffused regions of a second conductive type different from the first conductive type formed into a plurality of spaced columns extending in a first direction on one surface of the semiconductor substrate and having functions of bit lines; a plurality of columns of element isolation insulating films formed on the impurity diffused regions of the second conductive type, with active regions formed therebetween; a plurality of MOS transistors formed in the active regions aligned in each of a plurality of rows extending in a second direction substantially perpendicular to the first direction, each MOS transistor including a gate formed on a part of the active region with a gate insulating film therebetween and source and drain formed in the impurity diffused regions of the second conductive type; and word lines each connected electrically to the gates of the MOS transistors aligned in each of the rows and ex

Abstract: A semiconductor memory device to be used as a mask ROM having: a MOS transistor array having MOS transistors disposed in a matrix of rows and columns, the drain-source circuits of the MOS transistors in each row being serially connected; a row selecting decoder for selecting one of the rows; first and second column lines alternately disposed in the row direction, each first column line being connected to one end of the drain-source circuit of each of the MOS transistors disposed in one column, and each second column line being connected to the other end of the drain-source circuit of each of the MOS transistors disposed in the one column; a data reading circuit for reading data stored in the MOS transistor array; a first switching circuit for selectively connecting one of the first column lines to the data reading circuit; a second switching circuit for selectively connecting one of the second column lines to a ground potential; and a column selecting circuit for selecting one of the columns of the MOS transi

Abstract: An electrically programmable read only memory device accumulates electrons in a floating gate electrode so as to change the threshold level at a first control gate electrode capacitively coupled with the floating gate electrode, and a second control gate electrode is further capacitively coupled with the floating gate electrode through a composite gate insulating film structure implemented by a silicon nitride film sandwiched between silicon oxide films, when the electrons are evacuated from the floating gate electrode in ultra-violet radiation, the second control gate electrode is biased to a certain voltage level lower than a virgin threshold level provided upon completion of a fabricating process so that the threshold level is lowered rather than the virgin threshold level for speed up of a read-out operation.

Abstract: An improved structure of and a method of manufacturing a semiconductor device which comprises a semiconductor substrate of a first conductivity type, a gate region formed on one surface of the substrate and including a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode laminated in that order, source and drain diffusion layers formed on the one surface of the substrate with the gate region disposed between the source and drain diffusion layers, the source and drain diffusion layers having a second conductivity type different from the first conductivity type, and a diffusion layer of the first conductivity type formed in a selected region of the substrate including at least a part of an intermediate region disposed between the source and drain diffusion layers, the diffusion layer of the first conductivity type having an inclined impurity concentration higher than that of the substrate such that the concentration gradually decreases in the direction fr

Abstract: A non-volatile semiconductor memory comprises a P-type semiconductor substrate having an active region defined by a field isolation region, and a non-volatile memory cell composed of a floating gate N-channel transistor for programming and a floating gate P-channel transistor for reading. The floating gate N-channel transistor is formed in the active region of the substrate. The flaoting gate P-channel transistor includes a source region and a drain region both formed in a conductive semiconductor layer located in the field isolation region, a floating gate formed through an insulating layer above a portion of the conductive semiconductor layer between the source region and the drain region, and a control gate formed through an insulating layer above the floating gate. The floating gate of the P-channel transistor is formed of an extension of a floating gate of the N-channel transistor, and the control gate of the P-channel transistor is connected commonly to a control gate of the N-channel transistor.

Abstract: A non-volatile memory device is fabricated on a semiconductor substrate structure and comprises a word line formed by a buried layer in the semiconductor substrate structure and a plurality of memory cells associated with the word line, and each of the memory cells comprises a control gate region of formed in the semiconductor substrate structure and extending from the word line to a major surface portion of the semiconductor substrate structure, a first gate insulating film covering a top surface of the control gate region, a source region of formed in the major surface portion of the semiconductor substrate structure, a drain region formed in the major surface portion of the semiconductor substrate structure and spaced from the control gate region and the source region, a second gate insulating film provided over that area between the source and drain regions, and a floating gate electrode extending from the first gate insulating film to the second gate insulating film, since the word line extends below the

Abstract: An integrated circuit semiconductor device having an improved wiring structure is disclosed. An insulating film and a semiconductor layer are formed in sequence on an upper surface of a semiconductor body, and first and second wiring layers are formed in the semiconductor body and in the semiconductor layer, respectively. A plurality of circuit elements are formed in the semiconductor layer on the insulating film, and each of the elements is connected to the first and second wiring layers. When the elements are memory cells, the first wiring layers may be used as bit lines.

Abstract: An erasable programmable read only memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines associated with the rows of the memory cells, respectively, and a plurality of digit line pairs respectively associated with the columns of the memory cells, each of the digit line pairs consists of a first digit line for a reading out operation and a second digit line for a write in operation, and each memory cell comprises a series combination of a selecting transistor of an enhancement type and a reading out transistor of a depletion type coupled between the first digit line and a source of constant voltage level and a write-in transistor of the enhancement type coupled between the second digit line and the source of constant voltage level and higher in impurity concentration than the read-out transistor for production of a large amount of hot carriers, in which a floating gate is shared between the reading out transistor and the write-in transistor for injecting the