Abstract: A coplanar waveguide resonator (100a) has a center conductor (101) formed on a dielectric substrate (105) that has a line conductor (a center line conductor) (101b) extending in the input/output direction, a ground conductor (103) that is disposed on the dielectric substrate (105) across a gap section from the center conductor (101), and a line conductor (a base stub) (104) formed as an extension line from the ground conductor (103), and a part of the base stub (104) constitutes a line conductor (a first collateral line conductor) (104a) disposed in parallel with the center line conductor (101b).

Abstract: A power series predistorter of the present invention includes a delay path for delaying a signal, a distortion generation path having an N-th order distortion generator and a vector adjuster, a divider for dividing an input signal between the delay path and the distortion generation path, a combiner for combining the output signal of the delay path and the output signal of the distortion generation path, and a controller for controlling the vector adjuster. The controller includes a setting unit, a distortion component measurement unit, a minimum condition calculation unit, and a recording unit. The setting unit specifies the phase or amplitude value of the vector adjuster. The distortion component measurement unit measures the distortion component of a power amplifier.

Abstract: A switch is replaced with a parallel resonant circuit 4. More specifically, a variable resonator includes a line part 1 that includes one or more lines and has an annular shape, at least two parallel resonant circuits 4 capable of changing a characteristic, and at least three variable reactance blocks 2 capable of changing a reactance value, in which the parallel resonant circuits 4 are electrically connected to the line part 1 at one end thereof at different positions on the line part 1, and the variable reactance blocks 2 are electrically connected to the line part 1 at predetermined intervals based on an electrical length at a resonance frequency.

Abstract: A bias circuit includes: a bias supply terminal 800; a parallel capacitor 3 connected at one end thereof to the bias supply terminal 800 and grounded at the other end thereof; and a parallel circuit 3L connected in parallel with the parallel capacitor 3 and connected at one end thereof to the bias supply terminal 800. Let 2?N. The parallel circuit 3L includes: a direct-current power supply connection terminal 600; N parallel inductors 21 to 2N connected in series with each other between the bias supply terminal 800 and the direct-current power supply connection terminal 600; and N?1 series resonators 91 to 9N?1. Each series resonator 91 to 9N?1 includes: a resonant capacitor 71 to 7N?1 connected at one end thereof to a connecting point between adjacent parallel inductors; and a resonant inductor 81 to 8N?1 connected at one end thereof to the other end of the resonant capacitor 71 to 7N?1 and grounded at the other end thereof.

Abstract: In a distortion generation path of a power series predistorter, a frequency characteristic compensator that adjusts the frequency characteristic of a distortion component is provided in series with an odd-order distortion generator. The output of a power amplifier is divided to obtain an output signal of the power amplifier, the output signal of the power amplifier is down-converted by a down converter, and a distortion detector detects a distortion component in the down-converted signal of base band. The frequency characteristic of the distortion component is split into windows each having a band width of ?f by a distortion component frequency characteristic splitter, and the power of the distortion component in each window is detected. Based on the detected power, the frequency characteristic compensator adjusts a part of the frequency characteristic of the distortion component associated with each window.

Abstract: In a feedforward amplifier (200) including a signal cancellation circuit (10) and a distortion eliminating circuit (20), a harmonic reaction amplifier (130) is used as a main amplifier of the signal cancellation circuit. A controller (43) obtains an adjacent channel leakage power ratio (ACLR) and a power efficiency from an output of the feedforward amplifier (200) and controls the gate bias voltages of two transistors (33A and 33B) of the harmonic reaction amplifier (130) to maximize the power efficiency under the condition that the ACLR is less than or equal to a reference value.

Abstract: A power series digital predistorter and a distortion compensation control method for the power series digital predistorter are capable of adjusting the coefficients of a frequency characteristic compensator at high speed. A controller in the power series digital predistorter collectively sets adjustment amounts for the phases in bands in an N-th order frequency characteristic compensator; collectively sets adjustment amounts for the amplitudes in the bands in the N-th order frequency characteristic compensator; determines whether an index indicating the degree of cancellation of a distortion component generated in a power amplifier satisfies a preset condition; and, if the index does not satisfy the condition, performs control such that the adjustment amounts for the phases and the adjustment amounts for the amplitudes are set again.

Abstract: A power series digital predistorter includes a combiner which combines an output from a linear transmission path with an output from an odd-order distortion generating path, an analog-to-digital converter which converts a feedback signal from an output of a power amplifier to a digital feedback signal, an odd-order distortion vector control part which controls vector adjustment performed by an odd-order distortion vector adjusting part in the odd-order distortion generating path, a cancellation signal generating part which generates a cancellation signal from an input transmission signal, a combiner which is inserted in a feedback signal path and which combines the cancellation signal with a signal from the feedback signal path, and a cancellation signal control part which controls the cancellation signal generating part so that the cancellation signal suppresses a main signal component in the feedback signal at the combiner.

Abstract: A variable resonator has a dielectric substrate 2, an input/output line 3 formed on the dielectric substrate 2, a first resonator 4 that has one end connected to the input/output line 3 and the other end grounded, and a second resonator that has one end connected to the input/output line 3 at the point of connection of the one end of the first resonator 4 and the other end grounded via a terminal switch 7. When the terminal switch 7 is turned off, resonance occurs at a frequency at which the sum of the line lengths of the first resonator 4 and the second resonator 6 equals to a quarter of the wavelength. When the terminal switch 7 is turned on, resonance occurs at a frequency at which a half of the sum of the line lengths equals to a quarter of the wavelength.

Abstract: An irreversible circuit element is configured by including a magnetic substance, a plurality of central conductors L1 to L3, one ends of which are connected to different input/output ports, arranged on the magnetic substance so as to intersect each other while being insulated from each other, a first conductor P1 connected to the other ends of all the central conductors L1 to L3, a second conductor, a plurality of matching capacitors (each configured by C1 to C3) connecting the one end of the central conductors L1 to L3 and the second conductor and a variable matching mechanism V1, one end of which is connected or integrated with the second conductor, capable of changing reactance between the one end and the other end thereof.

Abstract: The present invention discloses a cryogenic receiving amplifier using a gallium nitride high electron mobility transistor (GaN HEMT) as an amplifying device in a cryogenic temperature environment. The cryogenic receiving amplifier includes an input matching circuit which makes an impedance matching between a gate of the amplifying device and an outside of an input terminal, a gate biasing circuit which applies a DC voltage to the gate of the amplifying device, an output matching circuit which makes an impedance matching between a drain of the amplifying device and an outside of an output terminal, and a drain biasing circuit which applies a DC voltage to the drain of the amplifying device. The cooled temperature is preferably set to 150 K or below, and the GaN HEMT may be illuminated with light of a blue LED.

Abstract: A signal switching device including a plurality of transmission paths connected to an input path, the signal switching device outputting a signal from the input path through one of the transmission paths, including a first variable impedance unit connected to a first transmission path, the first variable impedance unit including a first section formed from a superconducting material, the first section being set to a non-superconducting state when the signal is to be output through a second transmission path, the first section including a portion of a predetermined length at an input end, the portion having an area of a cross section less than an area of a cross section of the first section at an output end.

Abstract: A multiband matching circuit includes a first matching unit for converting an impedance in a signal path to Z0 in a first frequency band, and a second matching unit formed of a series matching section connected at one end in series with the first matching unit in the signal path, which is a transmission line whose characteristic impedance is equal to the matching impedance Z0 or a circuit equivalent to the transmission line at least in the first frequency band, and a parallel matching section connected at one end to the signal path at the other end of the series matching section and grounded at the other end. The parallel matching section is configured to open in impedance the connection point to the signal path in the first frequency band. The series matching section and the parallel matching section are designed to match an impedance in a second frequency band with Z0.

Abstract: A multiband matching circuit includes a first matching unit, a second matching unit, and a third matching unit, with all units being connected in series in a signal path. Matching with target impedance is established at a first frequency by appropriately designing the first matching unit and at a second frequency by appropriately designing the second and third matching units. The second matching unit and the third matching unit are designed to make the conversion ratio of the impedance viewed from the connection point between the second matching unit and the third matching unit to a circuit element to the target impedance smaller than the conversion ratio of the impedance viewed from the connection point between the first matching unit and the second matching unit to the circuit element to the target impedance, at the second frequency.

Abstract: A coplanar resonator which is comprised of a dielectric substrate, a center conductor formed in the surface thereof, and a ground conductor formed so as to surround the same center conductor, wherein the same center conductor is comprised of a main line conductor 31, formed by extension in a rectilinear shape, and auxiliary line conductors 32a and 32b bifurcating from at least one end of the same main line conductor, folding back and being extended on both sides of the main line conductor.

Abstract: The present invention has for its object to provide a matching circuit with multiband capability which can be reduced in size, even if the number of handled frequency bands rises. The matching circuit of the present invention comprises a load having frequency-dependent characteristics, a first matching block connected with one end to the load with frequency-dependent characteristics, and a second matching block formed by lumped elements connected in series to the first matching block. And then, when a certain frequency band is used, matching is obtained with the series impedance of the first matching block and the second matching block. When a separate frequency band is used, a ?-type circuit is constituted by connecting auxiliary matching blocks to both sides of the second matching block. Next, at the same frequency, by taking the combined impedance of this ?-type circuit and a load whose characteristics do not depend on the frequency to be Z0, the influence of the second matching block is removed.

Abstract: The present invention has for its object to provide a matching circuit with multiband capability which can be reduced in size, even if the number of handled frequency bands rises. The matching circuit of the present invention comprises a load having frequency-dependent characteristics, a first matching block connected with one end to the load with frequency-dependent characteristics, and a second matching block formed by lumped elements connected in series to the first matching block. And then, when a certain frequency band is used, matching is obtained with the series impedance of the first matching block and the second matching block. When a separate frequency band is used, a ?-type circuit is constituted by connecting auxiliary matching blocks to both sides of the second matching block. Next, at the same frequency, by taking the combined impedance of this ?-type circuit and a load whose characteristics do not depend on the frequency to be Z0, the influence of the second matching block is removed.

Abstract: A signal input/output line 101 is used for input and output of a signal. A first resonating part 102 is connected to the signal input/output line 101 at one end and is opened at the other end. A second resonating part 103 is connected to a ground conductor 105 at one end and is opened at the other end. A connecting line 104 has a predetermined length and is connected to a point of connection between the signal input/output line 101 and the first resonating part 102 at one end and is connected to a predetermined point on the second resonating part 103 at the other end.

Abstract: There is provided a matching circuit, in which a main-matching block and a sub-matching block are connected in series. The sub-matching block includes: a series matching block of which one end is connected to the main-matching block; and a parallel matching network connected to the other end of the series matching block. At a first frequency f1, the connection point of the series matching block and a first parallel matching block is caused to be in an open state for a radio-frequency signal, and the connection point of the first parallel matching block and the second parallel matching block is caused to be in a short state for the radio-frequency signal. Impedance matching is performed by the main-matching block and the series matching block at the first frequency f1, and is performed by the main-matching block and the sub-matching block at the second frequency f2.

Abstract: A power series predistorter of the present invention includes a delay path for delaying a signal, a distortion generation path having an N-th order distortion generator and a vector adjuster, a divider for dividing an input signal between the delay path and the distortion generation path, a combiner for combining the output signal of the delay path and the output signal of the distortion generation path, and a controller for controlling the vector adjuster. The controller includes a setting unit, a distortion component measurement unit, a minimum condition calculation unit, and a recording unit. The setting unit specifies the phase or amplitude value of the vector adjuster. The distortion component measurement unit measures the distortion component of a power amplifier.