Abstract: A biochemical process and apparatus for use in the process are described. The process comprises reacting (a) a hydrophobic substrate with (b) a solution or dispersion comprising a hydrophilic substrate and an enzyme catalyst, by contacting through a porous thin membrane, wherein the hydrophobic and hydrophilic substrates are incompatible with each other. The apparatus comprises a main body and a porous thin membrane provided inside the main body so as to define therein at least two channels, wherein a hydrophobic substrate and a solution or dispersion comprising hydrophilic substrate and an enzyme catalyst are contacted through the thin membrane by passing them through the respective channels.

Abstract: There is disclosed a digital integrated circuit device which has high-speed transistors of a selected type. A timing controller is incorporated in this device and performs timing control for an internal digital circuit. The timing controller includes a series-circuit of two flip-flop circuits serving as a frequency-dividing circuit for frequency-dividing a reference clock signal and generating an internal timing signal, and a switch circuit connected to a signal feedback line of these flip-flop circuits. In a normal mode, the switch circuit supplies the internal timing signal output from the flip-flop circuits to the digital integrated circuit. At a desired timing, the switch circuit performs a switching operation in response to a control signal, electrically disconnects the signal feedback line of the flip-flop circuits, and alternatively supplies an external timing signal externally supplied thereto to the digital integrated circuit.

Abstract: Disclosed is a logic circuit using Schottky barrier FETs comprising a plurality of circuits connected in series between first and second power supply terminals, the plurality of circuits being DCFL and/or SCFL circuits, the DCFL circuit containing a switching element and a load element, the elements being connected in a direct fashion, and consisting of Schottky barrier FETs, the SCFL circuit being a logic unit containing Schottky barrier FETs connected in a differential fashion, and a potential stabilizing means for stabilizing a potential at the junction point between the adjacent circuits, by supplementally feeding the differential current between the current consumed by the adjacent circuits.

Abstract: An analog-digital converter comprises a first comparing-converting device for comparing analog input voltages and a plurality of primary reference voltages at different levels, respectively, and converting the analog input voltages to digital signals on the most significant bit sides; a reference voltage generating device for generating a plurality of secondary reference voltages at different levels from the primary reference voltages supplied to both terminals of the reference voltage generating device; a switching device for supplying the primary reference voltage most close in sequential order to the analog input voltages to the reference voltage generating device in accordance with the compared results of the first comparing-converting device; a second comparing-converting device for converting the compared results between the analog input voltages and the secondary reference voltages to signals corresponding to digital signals on the least significant bit side with respect to the analog input voltages; a

Abstract: A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors.

Abstract: In an A/D converter in which a first comparator A/D converter for providing the most significant bits of a digital output and a second comparator A/D converter for providing the least significant bits of the digital output are cascaded, a switching circuit is provided between the first A/D converter and the second A/D converter. This switching circuit is responsive to the comparison between an analog input voltage and first comparison reference voltages in the first A/D converter to apply two adjacent first reference voltages between which the analog input voltages lies to both ends of a voltage dividing circuit network of the second A/D converter to thereby provide second comparison reference voltages. In the second A/D converter, the second comparison reference voltages are compared with the analog input voltage by comparators, to provide the least significant bits of a digital output.

Abstract: A logic circuit using depletion-mode field effect switching transistors, wherein, a plurality of logic elements respectively having at least one depletion-mode switching FET are connected in series. The source electrodes of the switching FETs are maintained at a voltage higher by a predetermined voltage than ground potential by the Schottky diode and connected commonly to each other. The switching FETs are connected at the drain electrodes through active loads to a power source terminal supplied with one type of external DC power source voltage. The drain potential of the switching FETs is level-shifted to a predetermined voltage higher than the gate potential of the FETs in the next stage. The FETs are provided between the diodes and ground to prevent the variation in the level shift voltage.

Abstract: A semiconductor chip including at least three variable capacity diodes for use at a frequency of 30 to 300 megaherzs is mounted on a grounding member so as to be sealed within a package. A plurality of external connection conductors each coupled to the diode and a plurality of external ground conductors coupled to the grounding member extend out of the package. Each ground conductor is disposed between the adjacent two of the external ground conductors. The arrangement permits a decrease of interference occurring due to a stray capacitance between the diodes.