Abstract: This disc brake includes a cylinder bore into which a piston is fitted, a seal groove provided in the cylinder bore as an annular groove, and a seal member which has a rectangular cross section shape and which is fitted into the seal groove and seal a space between the piston and the cylinder bore. The seal groove includes a bottom surface portion, a side surface portion, and a chamfered portion. The chamfered portion is formed to expand an opening of the seal groove in the axial direction of the cylinder bore and has two types of curvature radii (r1 and r2).

Abstract: A semiconductor device according to an embodiment includes: first and second gate electrodes; first and second spacer layers respectively covering the first and second gate electrodes; first and second liner layers respectively covering the first and second gate electrodes with the first and second spacer layers interposed therebetween; a first contact extending from above the first liner layer to below the first spacer layer and including a first conductive layer connected to the first gate electrode; and a second contact extending from above the second liner layer to below the second spacer layer and including a second conductive layer connected to the second gate electrode. The first conductive layer is in contact with the first spacer layer on the side surface via a first insulating layer covering a sidewall of the first conductive layer. The second conductive layer is in direct contact with the second spacer layer on the side surface.

Abstract: According to a certain embodiment, the nonvolatile semiconductor memory device includes: a first conductivity-type semiconductor substrate including a crushed layer on a back side surface thereof; a memory cell array disposed on a front side surface of the semiconductor substrate opposite to the crushed layer; and a first conductivity-type high voltage transistor HVP disposed on the semiconductor substrate and including a first conductivity-type channel, configured to supply a high voltage to the memory cell array. The first conductivity-type high voltage transistor includes: a well region NW disposed on the surface of the semiconductor substrate and having a second conductivity type; a source region and a drain region disposed in the well region; and a first conductivity-type first high concentration layer WT2 disposed between the crushed layer of the semiconductor substrate and the well region and having a higher concentration than an impurity concentration of the semiconductor substrate.

Abstract: According to a certain embodiment, the nonvolatile semiconductor memory device includes: a first conductivity-type semiconductor substrate including a crushed layer on a back side surface thereof; a memory cell array disposed on a front side surface of the semiconductor substrate opposite to the crushed layer; and a first conductivity-type high voltage transistor HVP disposed on the semiconductor substrate and including a first conductivity-type channel, configured to supply a high voltage to the memory cell array. The first conductivity-type high voltage transistor includes: a well region NW disposed on the surface of the semiconductor substrate and having a second conductivity type; a source region and a drain region disposed in the well region; and a first conductivity-type first high concentration layer WT2 disposed between the crushed layer of the semiconductor substrate and the well region and having a higher concentration than an impurity concentration of the semiconductor substrate.

Abstract: In a jig main body constructing a conduction inspection jig, a pin guard plate is arranged so as to be movable back and forth between the main body bottom portion and the main body guide portion. Before conduction inspection, the tip end of a conduction pin is positioned outside the conduction pin hole. When the pin guard plate moves towards a side of the main body bottom portion with a start of the conduction inspection, only the tip end of the normal conduction pin without bent enters into the conduction pin hole and penetrates, and thereby protrudes from the conduction pin hole. An inspection method of a conduction pin includes an arranging step of arranging the tip end outside the conduction pin hole, a moving step of moving the pin guard plate, and a detecting step of detecting whether or not the tip end enters into the conduction pin hole.

Abstract: In a jig main body constructing a conduction inspection jig, a pin guard plate is arranged so as to be movable back and forth between the main body bottom portion and the main body guide portion. Before conduction inspection, the tip end of a conduction pin is positioned outside the conduction pin hole. When the pin guard plate moves towards a side of the main body bottom portion with a start of the conduction inspection, only the tip end of the normal conduction pin without bent enters into the conduction pin hole and penetrates, and thereby protrudes from the conduction pin hole. An inspection method of a conduction pin includes an arranging step of arranging the tip end outside the conduction pin hole, a moving step of moving the pin guard plate, and a detecting step of detecting whether or not the tip end enters into the conduction pin hole.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory element including a first gate electrode having a first thickness disposed on a first insulation film on the semiconductor substrate, and a first peripheral element other than a memory element including a second gate electrode having a second thickness disposed on a second insulation film on the semiconductor substrate. The first gate electrode and second gate electrode comprise a plurality of film layers, and the configuration of the film layers are different as between the first gate electrode of the memory element and the second gate electrode of the peripheral element, and the first thickness is different from the second thickness.

Abstract: A semiconductor device according to an embodiment includes a first transistor and a second transistor. The first transistor is connected to a first wiring through a wiring plug made of a material having a first resistance value smaller than a predetermined value. In addition, at least any one of a drain and a source of the second transistor is connected to a second wiring through a polysilicon plug made of a material having a second resistance value larger than the first resistance value.

Abstract: A semiconductor memory device includes a memory cell, a peripheral circuit configured to drive the memory cell, and a protection element. The peripheral circuit includes a first p-type MOS transistor including a gate electrode and a gate insulating film having a first film thickness, a second p-type MOS transistor including a gate electrode and a gate insulating film having a second film thickness, and an n-type MOS transistor. The gate electrode of the first p-type MOS transistor is connected to the protection element. The gate electrodes included in the second p-type MOS transistor and the n-type MOS transistor are connected only to an impurity region of another transistor or only to a gate electrode of the another transistor.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate a memory element that includes a first gate electrode having a first height on the semiconductor substrate through a first insulation film, and a peripheral element other than the memory element that includes a second gate electrode having a second height on the semiconductor substrate through a second insulation film, in which stacked structures of gate materials are different between the first gate electrode of the memory element and the second gate electrode of the peripheral element, and the first height of the first gate electrode is different from the second height of the second gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate having a memory cell region and a peripheral circuit region, a plurality of adjacent memory gates formed on the semiconductor substrate via a tunnel insulating film in the memory cell region, a first insulating film covering the memory gates and having air gaps formed therein between the memory gates, a first barrier film on the first insulating film, a second insulating film above the semiconductor substrate in the peripheral circuit region, a second barrier film on the first barrier film and the second insulating film, and a third insulating film on the second barrier film and having first and second grooves, in which first and second wirings are respectively formed. A lower surface of the second wiring is closer to the upper surface of the semiconductor substrate in the peripheral circuit region than an upper surface of the second barrier film.

Abstract: In one implementation a display apparatus, a display area of a display screen of a display panel is defined by edge portions of a first window formed in a first frame body. The first frame body is formed from a thin synthetic resin sheet and has upper airflow passages and side airflow passages formed therein. An outer communication portion of each of the upper airflow passages and an outer communication portion of each of the side airflow passages are exposed inside holes formed in a second frame body disposed in front of the first frame body. An inner communication portion of the upper airflow passage and an inner communication portion of the side airflow passage are exposed inside the edge portions of a second window of the second frame body. A space formed between the display panel and a cover plate communicates with the outer space via the upper airflow passages and the side airflow passages.

Abstract: A first insulation film is on a substrate. A first resistance part is on the first insulation film. A boundary film is on the first resistance part. A second resistance part is on the boundary film. A second insulation film is on the second resistance part. A first conductive part and a second conductive part are on the second insulation film, and are isolated from each other. The first conductive part includes a first connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The second conductive part includes a second connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The first resistance part is connected to the first conductive part via the first connection part, and is connected to the second conductive part via the second connection part.

Abstract: In one implementation a display apparatus, a display area of a display screen of a display panel is defined by edge portions of a first window formed in a first frame body. The first frame body is formed from a thin synthetic resin sheet and has upper airflow passages and side airflow passages formed therein. An outer communication portion of each of the upper airflow passages and an outer communication portion of each of the side airflow passages are exposed inside holes formed in a second frame body disposed in front of the first frame body. An inner communication portion of the upper airflow passage and an inner communication portion of the side airflow passage are exposed inside the edge portions of a second window of the second frame body. A space formed between the display panel and a cover plate communicates with the outer space via the upper airflow passages and the side airflow passages.

Abstract: A first insulation film is on a substrate. A first resistance part is on the first insulation film. A boundary film is on the first resistance part. A second resistance part is on the boundary film. A second insulation film is on the second resistance part. A first conductive part and a second conductive part are on the second insulation film, and are isolated from each other. The first conductive part includes a first connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The second conductive part includes a second connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The first resistance part is connected to the first conductive part via the first connection part, and is connected to the second conductive part via the second connection part.

Abstract: A method of controlling the criticality of a nuclear fuel cycle facility includes steps of producing a reactor fuel by adding less than 0.1% by weight of gadolinia to a uranium dioxide powder with a uranium enrichment of greater than 5% by weight and controlling the effective neutron multiplication factor of a uranium dioxide system in a step of handling the reactor fuel to be less than or equal to the maximum of the effective neutron multiplication factor of a uranium dioxide system with a uranium enrichment of 5% by weight.

Abstract: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

Abstract: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.

Abstract: A nonvolatile semiconductor memory according to an example of the present invention includes first and second diffusion layers, a channel formed between the first and second diffusion layers, a gate insulating film formed on the channel, a floating gate electrode formed on the gate insulating film, an inter-gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-gate insulating film. An end portion of the inter-gate insulating film in a direction of channel length is on an inward side of a side surface of the floating gate electrode or a side surface of the control gate electrode.

Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate, and at least one memory cell formed on the semiconductor substrate, the at least one memory cell having a gate electrode unit in which a floating gate electrode and a control gate electrode are stacked, at least part of the control gate electrode being silicidated. The nonvolatile semiconductor storage device further includes at least one dummy transistor formed on the semiconductor substrate, the at least one dummy transistor having a first dummy electrode, and a second dummy electrode which has a current leakage path and which is stacked on the first dummy electrode.