Patents by Inventor Shoichi Watanabe

Shoichi Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200011920
    Abstract: In a jig main body constructing a conduction inspection jig, a pin guard plate is arranged so as to be movable back and forth between the main body bottom portion and the main body guide portion. Before conduction inspection, the tip end of a conduction pin is positioned outside the conduction pin hole. When the pin guard plate moves towards a side of the main body bottom portion with a start of the conduction inspection, only the tip end of the normal conduction pin without bent enters into the conduction pin hole and penetrates, and thereby protrudes from the conduction pin hole. An inspection method of a conduction pin includes an arranging step of arranging the tip end outside the conduction pin hole, a moving step of moving the pin guard plate, and a detecting step of detecting whether or not the tip end enters into the conduction pin hole.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 9, 2020
    Inventors: Shoichi Watanabe, Keigo Seki, Hiroshi Takeuchi
  • Patent number: 10466271
    Abstract: A scanning probe microscope includes: a cantilever; a cantilever supporting portion; a movement mechanism that moves a position of the cantilever; a light source that emits detection light; a detector that receives the detection light reflected on a reflecting surface of the cantilever; an objective lens; and a controller that controls the movement mechanism to perform a process including: detecting a spot position of a spot light of the detection light; detecting a position of the cantilever from an image captured by the imaging device; and controlling the movement mechanism based on the spot position, the position of the cantilever, an incident angle of the detection light, and the attachment angle such that the detection light is reflected on the reflecting surface when the cantilever is attached to the cantilever supporting portion.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: November 5, 2019
    Assignee: Hitachi High-Tech Science Corporation
    Inventors: Masafumi Watanabe, Toshihiro Ueno, Susumu Ito, Shoichi Hasegawa
  • Publication number: 20190176091
    Abstract: A first blood processing member 5U and a second blood processing member 5D are arranged in a first housing 2/U and a second housing 2/D, respectively. The first blood processing member 5U and the second blood processing member 5D are arranged in such a manner that inside filtration sections 5FI/U and 5FI/D face each other. A first blood chamber 2.1 is formed between the inside filtration sections 5FI/U and 5FI/D, and a second blood chamber 2.2 is formed between the inner periphery of the first housing 2/U and an outside filtration section 5FO/U and between the inner periphery of the second housing 2/D and an outside filtration section 5FO/D. A blood inlet port 7I communicates with the first blood chamber 2.1 (a blood inflow chamber 2IR), and a blood discharge port 7O communicates with the second blood chamber 2.2 (a blood outflow chambers 20R/U and 20R/D).
    Type: Application
    Filed: July 21, 2017
    Publication date: June 13, 2019
    Inventors: Masatoshi WATANABE, Shoichi GOTOH, Seiichi NAKAYA
  • Patent number: 10316108
    Abstract: An object of present invention is to provide a method for easily extracting and efficiently recovering xylan from wood. A xylan-containing material is produced by a method comprising steps of: (a) adding an acid and/or carbon dioxide to a black liquor discharged during a soda cooking step of wood chips including hardwood chips to adjust the pH of the black liquor to be in the range of 1 to 9, thereby giving a suspension; (b) dehydrating and washing an insoluble matter generated in the suspension to separately collect the insoluble matter; and (c) adding an organic solvent to the insoluble matter obtained at the step (b) to give a suspension, and separately collecting a xylan-containing material made of the insoluble matter present in the suspension by solid/liquid separation.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: June 11, 2019
    Assignee: NIPPON PAPER INDUSTRIES CO., LTD.
    Inventors: Shiho Tsuji, Masayuki Watanabe, Yutaka Nuruki, Shoichi Miyawaki
  • Patent number: 9530782
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory element including a first gate electrode having a first thickness disposed on a first insulation film on the semiconductor substrate, and a first peripheral element other than a memory element including a second gate electrode having a second thickness disposed on a second insulation film on the semiconductor substrate. The first gate electrode and second gate electrode comprise a plurality of film layers, and the configuration of the film layers are different as between the first gate electrode of the memory element and the second gate electrode of the peripheral element, and the first thickness is different from the second thickness.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: December 27, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazunari Toyonaga, Shoichi Watanabe, Karin Takayama, Shotaro Murata, Satoshi Nagashima
  • Publication number: 20160233163
    Abstract: A semiconductor device according to an embodiment includes a first transistor and a second transistor. The first transistor is connected to a first wiring through a wiring plug made of a material having a first resistance value smaller than a predetermined value. In addition, at least any one of a drain and a source of the second transistor is connected to a second wiring through a polysilicon plug made of a material having a second resistance value larger than the first resistance value.
    Type: Application
    Filed: June 5, 2015
    Publication date: August 11, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shoichi WATANABE, Kiyoshi OKUYAMA, Kimitoshi OKANO
  • Publication number: 20160019965
    Abstract: A semiconductor memory device includes a memory cell, a peripheral circuit configured to drive the memory cell, and a protection element. The peripheral circuit includes a first p-type MOS transistor including a gate electrode and a gate insulating film having a first film thickness, a second p-type MOS transistor including a gate electrode and a gate insulating film having a second film thickness, and an n-type MOS transistor. The gate electrode of the first p-type MOS transistor is connected to the protection element. The gate electrodes included in the second p-type MOS transistor and the n-type MOS transistor are connected only to an impurity region of another transistor or only to a gate electrode of the another transistor.
    Type: Application
    Filed: February 23, 2015
    Publication date: January 21, 2016
    Inventor: SHOICHI WATANABE
  • Publication number: 20150263014
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate a memory element that includes a first gate electrode having a first height on the semiconductor substrate through a first insulation film, and a peripheral element other than the memory element that includes a second gate electrode having a second height on the semiconductor substrate through a second insulation film, in which stacked structures of gate materials are different between the first gate electrode of the memory element and the second gate electrode of the peripheral element, and the first height of the first gate electrode is different from the second height of the second gate electrode.
    Type: Application
    Filed: February 9, 2015
    Publication date: September 17, 2015
    Inventors: Kazunari TOYONAGA, Shoichi WATANABE, Karin TAKAYAMA, Shotaro MURATA, Satoshi NAGASHIMA
  • Publication number: 20150263028
    Abstract: A semiconductor device includes a semiconductor substrate having a memory cell region and a peripheral circuit region, a plurality of adjacent memory gates formed on the semiconductor substrate via a tunnel insulating film in the memory cell region, a first insulating film covering the memory gates and having air gaps formed therein between the memory gates, a first barrier film on the first insulating film, a second insulating film above the semiconductor substrate in the peripheral circuit region, a second barrier film on the first barrier film and the second insulating film, and a third insulating film on the second barrier film and having first and second grooves, in which first and second wirings are respectively formed. A lower surface of the second wiring is closer to the upper surface of the semiconductor substrate in the peripheral circuit region than an upper surface of the second barrier film.
    Type: Application
    Filed: December 3, 2014
    Publication date: September 17, 2015
    Inventors: Shoichi WATANABE, Koichi MATSUNO
  • Patent number: 9095047
    Abstract: In one implementation a display apparatus, a display area of a display screen of a display panel is defined by edge portions of a first window formed in a first frame body. The first frame body is formed from a thin synthetic resin sheet and has upper airflow passages and side airflow passages formed therein. An outer communication portion of each of the upper airflow passages and an outer communication portion of each of the side airflow passages are exposed inside holes formed in a second frame body disposed in front of the first frame body. An inner communication portion of the upper airflow passage and an inner communication portion of the side airflow passage are exposed inside the edge portions of a second window of the second frame body. A space formed between the display panel and a cover plate communicates with the outer space via the upper airflow passages and the side airflow passages.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 28, 2015
    Assignee: Alpine Electronics, Inc.
    Inventor: Shoichi Watanabe
  • Patent number: 8921919
    Abstract: A first insulation film is on a substrate. A first resistance part is on the first insulation film. A boundary film is on the first resistance part. A second resistance part is on the boundary film. A second insulation film is on the second resistance part. A first conductive part and a second conductive part are on the second insulation film, and are isolated from each other. The first conductive part includes a first connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The second conductive part includes a second connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The first resistance part is connected to the first conductive part via the first connection part, and is connected to the second conductive part via the second connection part.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kuroe, Shoichi Watanabe
  • Publication number: 20130308252
    Abstract: In one implementation a display apparatus, a display area of a display screen of a display panel is defined by edge portions of a first window formed in a first frame body. The first frame body is formed from a thin synthetic resin sheet and has upper airflow passages and side airflow passages formed therein. An outer communication portion of each of the upper airflow passages and an outer communication portion of each of the side airflow passages are exposed inside holes formed in a second frame body disposed in front of the first frame body. An inner communication portion of the upper airflow passage and an inner communication portion of the side airflow passage are exposed inside the edge portions of a second window of the second frame body. A space formed between the display panel and a cover plate communicates with the outer space via the upper airflow passages and the side airflow passages.
    Type: Application
    Filed: March 8, 2013
    Publication date: November 21, 2013
    Inventor: Shoichi Watanabe
  • Publication number: 20120241845
    Abstract: A first insulation film is on a substrate. A first resistance part is on the first insulation film. A boundary film is on the first resistance part. A second resistance part is on the boundary film. A second insulation film is on the second resistance part. A first conductive part and a second conductive part are on the second insulation film, and are isolated from each other. The first conductive part includes a first connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The second conductive part includes a second connection part penetrating the second insulation film and the second resistance part and contacting a surface of the boundary film. The first resistance part is connected to the first conductive part via the first connection part, and is connected to the second conductive part via the second connection part.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki KUROE, Shoichi Watanabe
  • Patent number: 8130896
    Abstract: A method of controlling the criticality of a nuclear fuel cycle facility includes steps of producing a reactor fuel by adding less than 0.1% by weight of gadolinia to a uranium dioxide powder with a uranium enrichment of greater than 5% by weight and controlling the effective neutron multiplication factor of a uranium dioxide system in a step of handling the reactor fuel to be less than or equal to the maximum of the effective neutron multiplication factor of a uranium dioxide system with a uranium enrichment of 5% by weight.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: March 6, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoichi Watanabe, Ishi Mitsuhashi, Kenichi Yoshioka
  • Publication number: 20120037973
    Abstract: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.
    Type: Application
    Filed: October 25, 2011
    Publication date: February 16, 2012
    Inventors: Kenji GOMIKAWA, Tadashi Iguchi, Mitsuhiro Noguchi, Shoichi Watanabe
  • Patent number: 8072021
    Abstract: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Gomikawa, Tadashi Iguchi, Mitsuhiro Noguchi, Shoichi Watanabe
  • Patent number: 7804123
    Abstract: A nonvolatile semiconductor memory according to an example of the present invention includes first and second diffusion layers, a channel formed between the first and second diffusion layers, a gate insulating film formed on the channel, a floating gate electrode formed on the gate insulating film, an inter-gate insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-gate insulating film. An end portion of the inter-gate insulating film in a direction of channel length is on an inward side of a side surface of the floating gate electrode or a side surface of the control gate electrode.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: September 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shoichi Watanabe
  • Patent number: 7705393
    Abstract: A nonvolatile semiconductor storage device includes a semiconductor substrate, and at least one memory cell formed on the semiconductor substrate, the at least one memory cell having a gate electrode unit in which a floating gate electrode and a control gate electrode are stacked, at least part of the control gate electrode being silicidated. The nonvolatile semiconductor storage device further includes at least one dummy transistor formed on the semiconductor substrate, the at least one dummy transistor having a first dummy electrode, and a second dummy electrode which has a current leakage path and which is stacked on the first dummy electrode.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: April 27, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shoichi Watanabe
  • Publication number: 20090057749
    Abstract: A memory cell includes a floating gate electrode, a first inter-electrode insulating film and a control gate electrode. A peripheral transistor includes a lower electrode, a second inter-electrode insulating film and an upper electrode. The lower electrode and the upper electrode are electrically connected via an opening provided on the second inter-electrode insulating film. The first and second inter-electrode insulating films include a high-permittivity material, the first inter-electrode insulating film has a first structure, and the second inter-electrode insulating film has a second structure different from the first structure.
    Type: Application
    Filed: August 8, 2008
    Publication date: March 5, 2009
    Inventors: Kenji GOMIKAWA, Tadashi Iguchi, Mitsuhiro Noguchi, Shoichi Watanabe
  • Publication number: 20090028284
    Abstract: A method of controlling the criticality of a nuclear fuel cycle facility includes steps of producing a reactor fuel by adding less than 0.1% by weight of gadolinia to a uranium dioxide powder with a uranium enrichment of greater than 5% by weight and controlling the effective neutron multiplication factor of a uranium dioxide system in a step of handling the reactor fuel to be less than or equal to the maximum of the effective neutron multiplication factor of a uranium dioxide system with a uranium enrichment of 5% by weight.
    Type: Application
    Filed: May 14, 2008
    Publication date: January 29, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shoichi Watanabe, Ishi Mitsuhashi, Kenichi Yoshioka