Patents by Inventor Shoichiro Kawashima
Shoichiro Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050195639Abstract: A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.Type: ApplicationFiled: March 7, 2005Publication date: September 8, 2005Inventors: Isao Fukushi, Keizo Morita, Shoichiro Kawashima
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Publication number: 20050128784Abstract: A bit line is connected, via a first pMOS transistor, to a first node whose potential is set at a prescribed negative voltage in advance. The gate voltage of the first pMOS transistor is set at a constant voltage that is slightly lower than its threshold voltage. During a read operation, a current that flows into the bit line from a memory cell in accordance with a residual dielectric polarization value of a ferroelectric capacitor always leaks to the first node, whereby the potential of the first node increases. The logical value of data stored in the memory cell is judged on the basis of a voltage increase at the first node. Since no control circuit for keeping the potential of the first node at the ground potential during a read operation is necessary, the layout size and the power consumption of a ferroelectric memory can be decreased.Type: ApplicationFiled: February 7, 2005Publication date: June 16, 2005Inventors: Shoichiro Kawashima, Toru Endo, Tomohisa Hirayama
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Patent number: 6836426Abstract: A semiconductor memory device includes a memory cell, a signal line on which a potential responsive to data read from the memory cell appears, a potential detecting circuit which outputs a detection signal in response to detecting that the potential on the signal line exceeds a predetermined potential, and a sense amplifier which starts amplifying the potential on the signal line in response to the detection signal.Type: GrantFiled: February 26, 2004Date of Patent: December 28, 2004Assignee: Fujitsu LimitedInventors: Isao Fukushi, Shoichiro Kawashima
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Patent number: 6707703Abstract: A first electrode of a capacitor C1 is connected to an output node N0, and through a PMOS transistor switch SW1 to ground. A second electrode of the capacitor C1 is on one hand connected through a node N1 to the output of a switching circuit 11, and on the other hand connected through a capacitor C2 and a node N2 to the output of a switching circuit 12. A control circuit 13 controls so that (1) in a first step, a switch SW1 is turned on to couple the output node N0 to ground, and the output of the switching circuits 11 and 12 are coupled to the power supply voltage VDD and ground, respectively; (2) in a second step, the output of the switching circuit 12 is coupled to the voltage supply voltage VDD with the output of the switching circuit 11 being in a high impedance state; and (3) in a third step, the output of the switching circuit 11 is coupled to ground with the switch SW1 being off and the output of the switching circuit 12 being in a high impedance state.Type: GrantFiled: January 3, 2003Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventor: Shoichiro Kawashima
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Patent number: 6687151Abstract: An output node NO is, on one hand, connected through a PMOS transistor TP1 and an NMOS transistor TN1 to ground, and on the other hand, connected through a PMOS transistor TP2 and an NMOS transistor TN2 to a node N6 which is selectively set to ground and VDD. The output node NO is connected through a capacitor C1 to the input of a driving inverter 11 in order to step-up or step-down the voltage of the output node NO. When the output node NO is set to −1V, the control circuit 10 turns off the PMOS transistors TP1 and TP2. It is also allowed to connect the output node through a first PMOS transistor to a second PMOS transistor whose back gate is connected to a power supply voltage VDD, and to connect the back gate of the first PMOS transistor to one end of a current path thereof on the side of the second PMOS transistor.Type: GrantFiled: December 3, 2002Date of Patent: February 3, 2004Assignee: Fujitsu LimitedInventors: Toru Endo, Shoichiro Kawashima
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Patent number: 6661697Abstract: The present invention provides a data storage device that has high reliability and less power consumption, and a data read-out circuit and a data read-out method employed in the data storage device. This data storage device of the present invention includes a bit line and a memory cell (a ferroelectric capacitor) connected to the bit line. This data storage device characteristically further includes: a capacitor that accumulates electric charge supplied; a negative voltage generating circuit, a p-channel MOS transistor T2, a Vth generating circuit 11, and a feedback circuit 13 that transfer electric charge outputted onto the bit line BL at the time of data read-out to the capacitor; and a sense amplifier circuit 5 that amplifies a voltage generated by the electric charge accumulated by the capacitor, so as to read out the data from the memory cell.Type: GrantFiled: October 18, 2002Date of Patent: December 9, 2003Assignee: Fujitsu LimitedInventors: Akira Yamamoto, Shoichiro Kawashima
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Publication number: 20030146741Abstract: An output node NO is, on one hand, connected through a PMOS transistor TP1 and an NMOS transistor TN1 to ground, and on the other hand, connected through a PMOS transistor TP2 and an NMOS transistor TN2 to a node N6 which is selectively set to ground and VDD. The output node NO is connected through a capacitor C1 to the input of a driving inverter 11 in order to step-up or step-down the voltage of the output node NO. When the output node NO is set to −1V, the control circuit 10 turns off the PMOS transistors TP1 and TP2. It is also allowed to connect the output node through a first PMOS transistor to a second PMOS transistor whose back gate is connected to a power supply voltage VDD, and to connect the back gate of the first PMOS transistor to one end of a current path thereof on the side of the second PMOS transistor.Type: ApplicationFiled: December 3, 2002Publication date: August 7, 2003Applicant: FUJITSU LIMITEDInventors: Toru Endo, Shoichiro Kawashima
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Publication number: 20030128571Abstract: A first electrode of a capacitor C1 is connected to an output node NO, and through a PMOS transistor switch SW1 to ground. A second electrode of the capacitor C1 is on one hand connected through a node N1 to the output of a switching circuit 11, and on the other hand connected through a capacitor C2 and a node N2 to the output of a switching circuit 12. A control circuit 13 controls so that (1) in a first step, a switch SW1 is turned on to couple the output node NO to ground, and the output of the switching circuits 11 and 12 are coupled to the power supply voltage VDD and ground, respectively; (2) in a second step, the output of the switching circuit 12 is coupled to the voltage supply voltage VDD with the output of the switching circuit 11 being in a high impedance state; and (3) in a third step, the output of the switching circuit 11 is coupled to ground with the switch SW1 being off and the output of the switching circuit 12 being in a high impedance state.Type: ApplicationFiled: January 3, 2003Publication date: July 10, 2003Applicant: FUJITSU LIMITEDInventor: Shoichiro Kawashima
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Patent number: 6538915Abstract: A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.Type: GrantFiled: October 18, 2002Date of Patent: March 25, 2003Assignee: Fujitsu LimitedInventors: Toru Endo, Shoichiro Kawashima
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Publication number: 20030031059Abstract: A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.Type: ApplicationFiled: October 18, 2002Publication date: February 13, 2003Applicant: FUJITSU LIMITEDInventors: Toru Endo, Shoichiro Kawashima
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Publication number: 20030031042Abstract: The present invention provides a data storage device that has high reliability and less power consumption, and a data read-out circuit and a data read-out method employed in the data storage device. This data storage device of the present invention includes a bit line and a memory cell (a ferroelectric capacitor) connected to the bit line. This data storage device characteristically further includes: a capacitor that accumulates electric charge supplied; a negative voltage generating circuit, a p-channel MOS transistor T2, a Vth generating circuit 11, and a feedback circuit 13 that transfer electric charge outputted onto the bit line BL at the time of data read-out to the capacitor; and a sense amplifier circuit 5 that amplifies a voltage generated by the electric charge accumulated by the capacitor, so as to read out the data from the memory cell.Type: ApplicationFiled: October 18, 2002Publication date: February 13, 2003Applicant: FUJITSU LIMITEDInventors: Akira Yamamoto, Shoichiro Kawashima
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Patent number: 6487103Abstract: The present invention provides a data storage device that has high reliability and less power consumption, and a data read-out circuit and a data read-out method employed in the data storage device. This data storage device of the present invention includes a bit line and a memory cell (a ferroelectric capacitor) connected to the bit line. This data storage device characteristically further includes: a capacitor that accumulates electric charge supplied; a negative voltage generating circuit, a p-channel MOS transistor T2, a Vth generating circuit 11, and a feedback circuit 13 that transfer electric charge outputted onto the bit line BL at the time of data read-out to the capacitor; and a sense amplifier circuit 5 that amplifies a voltage generated by the electric charge accumulated by the capacitor, so as to read out the data from the memory cell.Type: GrantFiled: March 21, 2001Date of Patent: November 26, 2002Assignee: Fujitsu LimitedInventors: Akira Yamamoto, Shoichiro Kawashima
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Patent number: 6487130Abstract: A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.Type: GrantFiled: June 22, 2001Date of Patent: November 26, 2002Assignee: Fujitsu LimitedInventors: Toru Endo, Shoichiro Kawashima
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Publication number: 20020060930Abstract: A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.Type: ApplicationFiled: June 22, 2001Publication date: May 23, 2002Applicant: FUJITSU LIMITEDInventors: Toru Endo, Shoichiro Kawashima
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Publication number: 20020051376Abstract: The present invention provides a data storage device that has high reliability and less power consumption, and a data read-out circuit and a data read-out method employed in the data storage device. This data storage device of the present invention includes a bit line and a memory cell (a ferroelectric capacitor) connected to the bit line. This data storage device characteristically further includes: a capacitor that accumulates electric charge supplied; a negative voltage generating circuit, a p-channel MOS transistor T2, a Vth generating circuit 11, and a feedback circuit 13 that transfer electric charge outputted onto the bit line BL at the time of data read-out to the capacitor; and a sense amplifier circuit 5 that amplifies a voltage generated by the electric charge accumulated by the capacitor, so as to read out the data from the memory cell.Type: ApplicationFiled: March 21, 2001Publication date: May 2, 2002Applicant: FUJITSU LIMITEDInventors: Akira Yamamoto, Shoichiro Kawashima
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Patent number: 6292408Abstract: A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line.Type: GrantFiled: January 7, 2000Date of Patent: September 18, 2001Inventors: Shoichiro Kawashima, Toshihiko Mori, Makoto Hamaminato
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Patent number: 6292418Abstract: A semiconductor memory device includes a memory cell, and a dynamic latch type sense amplifier including transistors that form not only a dynamic latch circuit which holds or releases data but also charge transfer gates via which charges are applied to or received from bit lines. Data is read from the cell connected to the bit lines at a same time as a precharging operation on the bit lines.Type: GrantFiled: November 25, 1998Date of Patent: September 18, 2001Assignee: Fujitsu LimitedInventors: Shoichiro Kawashima, Isao Fukushi
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Patent number: 6061276Abstract: A semiconductor memory device which can reduce a power consumption by reducing a charging and discharging current for a gate capacity of a transistor used for pulling up a bit line which constitutes a write recovery circuit. A pair of first and second bit lines are connected to a memory cell. A potential of one of the first and second bit lines is decreased during a write cycle in accordance with write data. A first loading element is connected between a power source line and the first bit line. The power source line supplies a positive power source voltage. A second loading element is connected between the power source line and the second bit line. A first transistor is provided for pulling up the first bit line. The first transistor has a current input terminal connected to the power source line and a current output terminal connected to the first bit line. A second transistor is provided for pulling up the second bit line.Type: GrantFiled: January 26, 1998Date of Patent: May 9, 2000Assignee: Fujitsu LimitedInventors: Shoichiro Kawashima, Toshihiko Mori, Makoto Hamaminato
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Patent number: 5936881Abstract: A semiconductor memory device includes cells arranged in a matrix formation. Each of the cells includes a driver transistor, a read transistor which is controlled by a read word line and outputs read data read from the cell to a read bit line, a write transistor which is controlled by a write word line and supplies write data supplied from a write bit line to a cell capacitor connected to a gate of the driver transistor, and a column write select transistor which is controlled by a column write select signal line and is connected to the write transistor in series. The write data is supplied to the cell capacitor via both the column write select transistor and the write transistor.Type: GrantFiled: August 18, 1998Date of Patent: August 10, 1999Assignee: Fujitsu LimitedInventors: Shoichiro Kawashima, Ryuhei Sasagawa, Makoto Hamaminato
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Patent number: 5740102Abstract: A semiconductor memory device includes a memory unit having a plurality of memory cells, Each memory cell includes a flip-flop circuit having driver transistors, as a data retention circuit. The device further includes a threshold voltage control unit for controlling respective threshold voltages of the driver transistors. When the device is in its accessed state, the threshold voltage control unit controls at least each threshold voltage of driver transistors constituting a selected memory cell to be a first threshold voltage. When the device is in its stand-by state, the threshold voltage control unit controls threshold voltages of all of respective driver transistors constituting each memory cell to be a second threshold voltage different from the first threshold voltage. By the constitution, it is possible to realize a stable data retention operation under the condition of a lower power supply voltage, and to reduce a dissipated power in a stand-by state.Type: GrantFiled: November 22, 1996Date of Patent: April 14, 1998Assignee: Fujitsu LimitedInventor: Shoichiro Kawashima