Abstract: A amplifier coupled to first and second power supply lines includes a first pair of cross-coupled transistors connected to the first power supply line and a pair of output terminals, and a second pair of cross-coupled transistors connected to the second power supply line. The amplifier includes a reset circuit which is provided between the first and second pairs of cross-coupled transistors and shortcircuits the pair of output terminals in response to a pair of predetermined control signals. The amplifier includes a pair of input transistors connected to the second pair of cross-coupled transistors, and a pair of non-linear elements which are provided between the first and second pairs of cross-coupled transistors.

Abstract: A semiconductor device has a plurality of transistor pairs. Each transistor pair includes a p-channel current path having a pair of p-type current terminal regions arranged by sandwiching a high resistivity first channel region and an n-channel current path having a pair of n-type current terminal regions arranged by sandwiching a high resistivity second channel region. The first channel region and the second channel region exert electric fields on each other by their intrinsic charges and are adjacently arranged so as to serve as a gate. A semiconductor memory device includes a memory element formed by first and second thin film semiconductor layers each including a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type sandwiching a channel region. A backgate is disposed in a faced relation to the channel region of one of the first and second thin film semiconductor layers which are laminated one atop the other.

Abstract: A semiconductor memory device includes a memory unit having a plurality of memory cells. Each memory cell includes a flip-flop circuit having driver transistors, as a data retention circuit. The device further includes a threshold voltage control unit for controlling respective threshold voltages of the driver transistors. When the device is in its accessed state, the threshold voltage control unit controls at least each threshold voltage of driver transistors constituting a selected memory cell to be a first threshold voltage. When the device is in its stand-by state, the threshold voltage control unit controls threshold voltages of all of respective driver transistors constituting each memory cell to be a second threshold voltage different from the first threshold voltage. By the constitution, it is possible to realize a stable data retention operation under the condition of a lower power supply voltage, and to reduce a dissipated power in a stand-by state.

Abstract: A semiconductor device has a plurality of transistor pairs. Each transistor pair includes a p-channel current path having a pair of p-type current terminal regions arranged by sandwiching a high resistivity of a first channel region, an n-channel current path having a pair of n-type current terminal regions arranged by sandwiching a high resistivity of a second channel region. The first channel region and the second channel region exert each electric field on each other by their intrinsic charges and are adjacently arranged so as to serve as a gate.

Abstract: A flip-flop type amplifier circuit is adapted to amplify a voltage difference between a first voltage and a second voltage. This amplifier circuit includes a first power line supplying a first power supply voltage, a second power line supplying a second power supply voltage lower than the first power supply voltage, a flip-flop circuit including first through fourth nodes, and first and second inverters coupled in a ring. The first node couples an input of the first inverter and an output of the second inverter and receiving the first voltage, and the second node couples an output of the first inverter and an input of the second inverter and receives the second voltage. A first impedance element is coupled between the first power line and the third node of the flip-flop circuit, and a second impedance element is coupled between the second power line and the fourth node of the flip-flop circuit.

Abstract: In a semiconductor device fabrication process, a so-called alignment mark or position-alignment mark, a laser trimmer are used. The position-alignment mark makes a considerable difference in amount between a vertically reflected laser beam light from the position-alignment mark and that from the background thereof to strengthen a contrast between the position-alignment mark and the background surrounding the mark, so that a signal-to-noise ratio (SN ratio) is considerably improved to enable a precise position alignment to be performed in the semiconductor device fabrication process. The position-alignment mark comprises: a position-detecting target having high reflectance; and a pair of low-reflectance regions which sandwich the position-detecting target therebetween.

Abstract: A level shift amplifier has first to n th inverters connected in series, with each positive voltage terminal of the first to n th inverter is connected to the first source line. Each negative voltage terminal of the first to (n-2)th inverter is connected to output of the second next inverter, respectively. The negative voltage terminal of the (n-1)th inverter is connected to a part of the output of the n th inverter, and the negative voltage terminal of the n th inverter is connected to the second source line. n pieces of feedback elements are connected between the input and output of each inverter. When a feedback element is established so that the gain of each inverter can be maximized, a self-bias amplifier circuit is composed. All inverters are driven by the self-bias voltage. The fine amplitude signals input to the first inverter become the output voltage of full amplitude between the first and second source lines in the n-th inverter.

Abstract: In a static type semiconductor memory device having a memory cell, the memory cell includes a flip-flop which has first and second nodes, a first transfer gate transistor which is connected between a first bit line of a pair of complementary bit lines and the first node, a second transfer gate transistor which is connected between a second bit line of the pair of complementary bit lines and the second node, a first capacitor which is connected between a word line and the gate of the first transfer gate, and a second capacitor which is connected between the word line and the gate of the second transfer gate. By the structure, even if the cell ratio is made small, it is possible to achieve stable operation at a low operating voltage and possible, thereby, to achieve both low power consumption and a high degree of integration.

Abstract: A pulse generator includes a first current control circuit, and a first transistor having a source coupled to a first power supply line via the first current control circuit, a drain and a gate. A second transistor has a gate connected to the gate of the first transistor, a drain connected to the drain of the first transistor, and a source connected to a second power supply line. The second transistor has a conduction type different from that of the first transistor. An input terminal is connected to the gates of the first and second transistors. An input signal is applied to the input terminal. An output terminal is connected to the first current control circuit. An output pulse indicative of a change in the input signal is output via the output terminal.

Abstract: A static random access memory comprises a memory cell array, a plurality of bit lines provided in correspondence to said plurality of memory cell columns, a first decoder for selecting a memory cell column, a second decoder for selecting a memory cell groups included in the selected memory cell column, and a third decoder supplied for selecting a memory cell included in the selected memory cell group. Each memory cell comprises a flip-flop circuit that is formed of thin film transistors. Each memory cell group includes a predetermined number of the memory cells, a sub-bit line extending over the memory cells included in the memory cell group, a first selection circuit connected to the sub-bit line and further to the bit line that corresponds to the selected memory cell group and a second selection circuit connected to the sub-bit line and the bit line that corresponds to the selected memory cell group.

Abstract: A semiconductor memory circuit includes a variable delay circuit for delaying write data supplied from an external circuit such as a CPU by a delay time which is variably determined depending on a potential level of a write enable signal which is supplied from the external circuit and enables a write amplifier to write a delayed write data supplied from the delay circuit into a memory cell array.