Abstract: For scanning electron beams and measuring overlay misalignment between an upper layer pattern and a lower layer pattern with high precision, electron beams are scanned over a region including a first pattern and a second pattern of a sample, the sample having the lower layer pattern (the first pattern) and the upper layer pattern (the second pattern) formed in a step after a step of forming the first pattern. The electron beams are scanned such that scan directions and scan sequences of the electron beams become axial symmetrical or point-symmetrical in a plurality of pattern position measurement regions defined within the scan region for the electron beams, thereby reducing measurement errors resulting from the asymmetry of electric charge.

Abstract: A charged particle beam apparatus makes it possible to acquire information in the cross-sectional direction (depth direction) of a sample having an internal structure in a nondestructive manner with reduced damage. Further, the apparatus makes it possible to analyze the depth and/or dimensions in the depth direction of the internal structure. The charged particle beam apparatus includes: a means for providing a time base for control signals; a means for applying a charged particle beam to a sample in synchronization with the time base and controlling an irradiation position; a means for analyzing the emission characteristics of an emission electron from the sample from a detection signal of the emission electron; and a means for analyzing the electrical characteristics or cross-sectional morphological characteristics of the sample based on the emission characteristics.

Abstract: For scanning electron beams and measuring overlay misalignment between an upper layer pattern and a lower layer pattern with high precision, electron beams are scanned over a region including a first pattern and a second pattern of a sample, the sample having the lower layer pattern (the first pattern) and the upper layer pattern (the second pattern) formed in a step after a step of forming the first pattern. The electron beams are scanned such that scan directions and scan sequences of the electron beams become axial symmetrical or point-symmetrical in a plurality of pattern position measurement regions defined within the scan region for the electron beams, thereby reducing measurement errors resulting from the asymmetry of electric charge.

Abstract: A charged particle beam apparatus makes it possible to acquire information in the cross-sectional direction (depth direction) of a sample having an internal structure in a nondestructive manner with reduced damage. Further, the apparatus makes it possible to analyze the depth and/or dimensions in the depth direction of the internal structure. The charged particle beam apparatus includes: a means for providing a time base for control signals; a means for applying a charged particle beam to a sample in synchronization with the time base and controlling an irradiation position; a means for analyzing the emission characteristics of an emission electron from the sample from a detection signal of the emission electron; and a means for analyzing the electrical characteristics or cross-sectional morphological characteristics of the sample based on the emission characteristics.

Abstract: The present invention provides an electron beam measurement technique for measuring the shapes or sizes of portions of patterns on a sample, or detecting a defect or the like. An electron beam measurement apparatus has a unit for irradiating the patterns delineated on a substrate by a multi-exposure method, and classifying the patterns in an acquired image into multiple groups according to an exposure history record. The exposure history record is obtained based on brightness of the patterns and a difference between white bands of the patterns.

Abstract: Systems and methods using imaged device patterns to measure overlay between different layers in a semiconductor manufacturing process, such as a double-patterning process. Images of pattern features are acquired by scanning electron microscopy. The position of a patterning layer is determined using positions of pattern features for the patterning layer in the images. A relative position of each patterning layer with respect to other pattern features or patterning layers is determined in vector form based on the determined pattern positions. Overlay error is determined based on a comparison of the relative position with reference values from design or simulation. Overlay can be measured with high precision and accuracy by utilizing pattern symmetry.

Abstract: Systems and methods using imaged device patterns to measure overlay between different layers in a semiconductor manufacturing process, such as a double-patterning process. Images of pattern features are acquired by scanning electron microscopy. The position of a patterning layer is determined using positions of pattern features for the patterning layer in the images. A relative position of each patterning layer with respect to other pattern features or patterning layers is determined in vector form based on the determined pattern positions. Overlay error is determined based on a comparison of the relative position with reference values from design or simulation. Overlay can be measured with high precision and accuracy by utilizing pattern symmetry.

Abstract: A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.

Abstract: The present invention provides an electron beam measurement technique for measuring the shapes or sizes of portions of patterns on a sample, or detecting a defect or the like. An electron beam measurement apparatus has a unit for irradiating the patterns delineated on a substrate by a multi-exposure method, and classifying the patterns in an acquired image into multiple groups according to an exposure history record. The exposure history record is obtained based on brightness of the patterns and a difference between white bands of the patterns.

Abstract: The present invention provides an electron beam measurement technique for measuring the shapes or sizes of portions of patterns on a sample, or detecting a defect or the like. An electron beam measurement apparatus has a unit for irradiating the patterns delineated on a substrate by a multi-exposure method, and classifying the patterns in an acquired image into multiple groups according to an exposure history record. The exposure history record is obtained based on brightness of the patterns and a difference between white bands of the patterns.

Abstract: A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.

Abstract: The present invention provides an electron beam measurement technique for measuring the shapes or sizes of portions of patterns on a sample, or detecting a defect or the like. An electron beam measurement apparatus has a unit for irradiating the patterns delineated on a substrate by a multi-exposure method, and classifying the patterns in an acquired image into multiple groups according to an exposure history record. The exposure history record is obtained based on brightness of the patterns and a difference between white bands of the patterns.

Abstract: The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.

Abstract: In a massed region of each of a plurality of transfer areas of a mask a plurality of light transmission patterns are formed by opening a half-tone film. A phase shifter is disposed in each of the light transmission patterns so that a 180° phase inversion occurs between the lights that transmit through adjacent light transmission patterns. In a sparse region of the plurality of transfer areas a solitary light transmission pattern is formed by opening the half-tone film. Both shape and size are the same among the light transmission patterns, which are disposed symmetrically in both the massed and sparse regions about the center between the transfer areas. The phase shifters in the massed regions are disposed so that the phase of each phase shifter in one of the transfer areas comes to be opposed to that of its counterpart in the other transfer area. In the exposure process, those transfer areas are overlaid one upon another in the same chip region.

Abstract: A compressor having a housing formed by a plurality of housing members that are connected together is disclosed. The compressor is configured in such a manner that refrigerant is compressed in the housing and discharged to the exterior. Each of the housing members contains 9 to 17 percent by mass of Si, 3.5 to 6 percent by mass of Cu, 0.2 to 1.2 percent by mass of Mg, 0.2 to 1.5 percent by mass of Fe, 0 to 1 percent by mass of Mn, 0.5 percent by mass or less of Ni, and a remaining portion containing Al and unavoidable impurities. It is preferred that the average hardness of each housing member is adjusted to HV130 to HV170 through solution heating in which the housing member is maintained at the treatment temperature of 450° C. to 510° C. for 0.5 hours or longer, followed by water quenching, and then by aging treatment in which the housing member is maintained at the treatment temperature of 170° C. to 230° C. for one to twenty-four hours after the c housing member is cast.

Abstract: A cast aluminum alloy excellent in the relaxation resistance property, comprising 9 to 17% by mass of Si, 3 to 6% by mass of Cu, 0.2 to 1.2% by mass of Mg, 0.2 to 1.5% by mass of Fe, 0.1 to 1% by mass of Mn, a balance consists of Al and unavoidable impurities, wherein a Ni content is not more than 0.5% by mass. The average hardness is adjusted to HV130 to HV160 by performing, after casting, solution heating by retaining the alloy at a treatment temperature of 450 to 510° C. for 0.5 hour or longer, performing water quenching and, thereafter, performing aging treatment by retaining the alloy at a treatment temperature of 170 to 230° C. for 1 to 24 hours.

Abstract: The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.

Abstract: The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.

Abstract: A method of fabrication of a semiconductor integrated circuit device uses a mark having, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of light transmitted through the second light transmitting region relative to light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region. The second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, said light shielding region is formed by a second film deposited over the first main surface of the mask substrate via said first film, and at least one of said first film and second is formed from a resist film.

Abstract: The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.