Abstract: Embodiments of the present invention provide systems and methods for storing calibration data for a test system operable to test a device under test (DUT). The test system includes one or more channel modules and a device interface. A first part of the calibration data is stored on a non-volatile memory. The non-volatile memory can be disposed in different parts of the test system. The non-volatile memory is located on the device interface and can also be located on one or more of the channel modules, as well as an attachment of the test system. The non-volatile memory is associated with the one or more channel modules. The second part of the calibration data is stored on a non-volatile memory associated with the device-under-test interface.

Abstract: Provided is an exposure apparatus that exposes a pattern on a sample, the exposure apparatus including a plurality of blanking electrodes that are provided corresponding to a plurality of charged particle beams and each switch whether the corresponding particle beam irradiates the sample according to an input voltage; an irradiation control section that outputs switching signals for switching blanking voltages supplied respectively to the blanking electrodes; and a measuring section that, for each blanking electrode, measures a delay amount that is from when the switching signal changes to when the blanking voltage changes.

Abstract: Provided is an exposure apparatus that exposes a pattern on a sample, the exposure apparatus including a plurality of blanking electrodes that are provided corresponding to a plurality of charged particle beams and each switch whether the corresponding particle beam irradiates the sample according to an input voltage; an irradiation control section that outputs switching signals for switching blanking voltages supplied respectively to the blanking electrodes; and a measuring section that, for each blanking electrode, measures a delay amount that is from when the switching signal changes to when the blanking voltage changes.

Abstract: Provided are a first test substrate and a second test substrate opposing each other, a first test circuit testing a device under test and being disposed on a face of the first test substrate that faces the second test substrate, a second test circuit testing the device under test and being disposed on a face of the second test substrate that faces the first test substrate, and a sealing section that is formed by sealing a space between the first test substrate and the second test substrate to enclose the first test circuit and the second test circuit in a common space that is filled with coolant.

Abstract: N upper-side resistors and N lower-side resistors are severally associated with respective bits of a digital input code. Each resistance value is weighted in an essentially binary manner according to the corresponding bit. N upper-side switches are each arranged in parallel with a corresponding upper-side resistor, and each is configured such that its on/off state is controlled according to the corresponding bit. N lower-side switches are each arranged in parallel with a corresponding lower-side resistor, and each is configured such that its on/off state is controlled according to logical inversion of the corresponding bit.

Abstract: A comparison judgment circuit judges the level of a signal received, via a transmission line, from a second device which is a communication partner. An input/output terminal is connected to the transmission line. An attenuator circuit attenuates the voltage at the input/output terminal so as to generate an attenuated voltage. A level comparator compares the attenuated voltage with a predetermined threshold voltage, and generates a level judgment signal that corresponds to the comparison result. A protection circuit monitors the voltage at the input/output terminal or the attenuated voltage. When the voltage to be monitored deviates from a predetermined voltage range, the protection circuit forcibly cuts off or changes the voltage input to the level comparator.

Abstract: A multi-valued driver circuit selectively outputs, to a transmission line, one from among multiple voltages according to a selection signal. A memory circuit stores setting data which define the respective levels of the multiple voltages. According to the selection signal, a selector circuit selects one from among the multiple setting data stored in the memory circuit. A Thevenin termination circuit outputs a voltage that corresponds to the upper M bits of the data thus selected by the selector circuit. An R-2R ladder circuit outputs a voltage that corresponds to the lower Nl bits of the data thus selected by the selector circuit.

Abstract: A test apparatus includes: a driver circuit that supplies, to a device under test, a test signal corresponding to an input signal; and a judging section that judges pass/fail of the device under test, based on the load voltage or the load current supplied to the device under test when supplying a test signal of a constant current or a constant voltage to the device under test from the driver circuit, where the driver circuit includes: a driver section that outputs the test signal; a supply current detecting section that detects a supply current supplied to the driver section; and an output control section that controls a voltage or a current of the test signal outputted from the driver section to the predetermined value, based on the supply current detected by the supply current detecting section.

Abstract: A differential SR flip-flop 100 receives a set signal S and a reset signal R, and generates a differential output pair Q and #Q. A first flip-flop FF1 generates a non-inverted output signal Q1 and an inverted output signal #Q1. A second flip-flop FF2 generates a non-inverted output signal Q2 and an inverted output signal #Q2. An averaging circuit 10 averages one output signal (Q1) of the first flip-flop FF1 and one output signal (Q2) of the second flip-flop FF2 so as to generate a first output signal Q3, and averages the other output signal (#Q1) of the first flip-flop FF1 and the other output signal (#Q2) of the second flip-flop FF2 so as to generate a second output signal #Q3. As a differential output pair, the differential SR flip-flop 100 outputs a signal that corresponds to the first output signal Q3 and a signal that corresponds to the second output signal #Q3.

Abstract: An input priority determination circuit is configured such that: (i) when a set signal S is asserted and a reset signal R is negated, an intermediate set signal S? is asserted and an intermediate reset signal R? is negated; (ii) when the set signal S is negated and the reset signal R is asserted, the intermediate set signal S? is negated, and the intermediate reset signal R? is asserted; (iii) when a control signal P indicates a set priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is asserted and the intermediate reset signal R? is negated; and (iv) when the control signal P indicates a reset priority mode, and when the set signal S and the reset signal R are both asserted, the intermediate set signal S? is negated and the intermediate reset signal R? is asserted.

Abstract: A test apparatus that tests a device under test, including a signal input section that supplies a test signal to a device under test (DUT) and a judging section that judges acceptability of the DUT based on a response signal output by the DUT in response to the test signal. The signal input section includes an operation circuit that generates the test signal and a power supply stabilizing circuit provided in the same chip to stabilize power supply voltage supplied to the operation circuit. The power supply stabilizing circuit includes a high-speed compensating section compensating for a change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed, and as low-speed compensating section compensating for the change in the power supply voltage supplied to the operation circuit, at a predetermined compensation speed lower than that of the high-speed compensating section.

Abstract: An equalizer circuit receives digital amplitude data A[N] which represents the amplitude level of the N-th (N is a nonnegative integer) signal to be transmitted via a transmission line and timing data T[N] which represents the cycle of the signal, and performs waveform shaping. The equalizer circuit includes: M (M is an integer) calculation units ECU1 through ECUm; and an adder ADD1 which adds the output data of the M calculation units ECU1 through ECUM and the amplitude data A[N] together so as to generate equalized amplitude data D[N]. A step response waveform RSTEP(t) for the transmission line is approximated by Expression RSTEP(t)=SSTEP(t)·(1?Sj=1:M fj(t)) using M (M is an integer of 2 or more) functions fj(t) (1?j?M) and a step waveform SSTEP(t) with the time t as an argument. The representative value of the function fj(t) in a range between T1 and T2 is represented by a function gj(T1, T2).

Abstract: A quadrature amplitude modulator is provided. An oscillator generates an in-phase carrier signal having a rectangular wave, a trapezoidal wave or a waveform similar to these, and a quadrature carrier signal, the phase of which is shifted by ¼ cycle relative to the in-phase carrier signal. A multi-level driver generates an in-phase modulated signal by amplitude modulating the in-phase carrier signal with an analog in-phase baseband signal having a discrete voltage level or current level in accordance with the in-phase baseband data. Likewise, the multi-level driver generates a quadrature modulated signal by amplitude modulating the quadrature carrier signal with an analog quadrature baseband signal having a discrete voltage level or current level in accordance with the quadrature baseband data The multi-level driver generates a modulated signal, the amplitude of which takes a discrete level, by combining the modulated signals together.

Abstract: An image processing device that processes input image data includes: an image dividing unit that divides the input image data into a plurality of blocks; an image type determining unit that determines the type of the input image data for every block on the basis of the number of edge elements included in the block; a frequency component conversion unit that converts color components of the input image data into frequency components for every block; and an image compression unit that compresses corresponding image data for every block by specifying unnecessary components of the converted frequency components of the image data on the basis of the determined type of the image data and suppressing or removing the specified unnecessary components.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.

Abstract: A power source stabilization circuit provided within a chip of an electronic device is provided. The power source stabilization circuit stabilizes a power source voltage supplied to an operational circuit of the electronic device. The power source stabilization circuit includes an amplifier that detects a fluctuation component in the power source voltage occurring in a main power source wiring used to supply the power source voltage to the operational circuit, amplifies the detected fluctuation component, and outputs the amplified fluctuation component, and a stabilization capacitor that is provided between an output end of the amplifier and the main power source wiring and supplies to the main power source wiring a current to reduce fluctuation in the power source voltage occurring in the main power source wiring, in accordance with the output from the amplifier.

Abstract: A multi-valued driver circuit selectively outputs, to a transmission line, one from among multiple voltages according to a selection signal. A memory circuit stores setting data which define the respective levels of the multiple voltages. According to the selection signal, a selector circuit selects one from among the multiple setting data stored in the memory circuit. A Thevenin termination circuit outputs a voltage that corresponds to the upper M bits of the data thus selected by the selector circuit. An R-2R ladder circuit outputs a voltage that corresponds to the lower Nl bits of the data thus selected by the selector circuit.

Abstract: N upper-side resistors and N lower-side resistors are severally associated with respective bits of a digital input code. Each resistance value is weighted in an essentially binary manner according to the corresponding bit. N upper-side switches are each arranged in parallel with a corresponding upper-side resistor, and each is configured such that its on/off state is controlled according to the corresponding bit. N lower-side switches are each arranged in parallel with a corresponding lower-side resistor, and each is configured such that its on/off state is controlled according to logical inversion of the corresponding bit.

Abstract: A first current source supplies a tail current It to a plurality of differential pairs. A pre-driver outputs gate signals to the gates of transistors of the corresponding differential pair. A pre-driver is configured to switch the state between the enable state and the disable state. In the enable state, the pre-driver outputs the gate signals that correspond to the differential signals. In the disable state, the pre-driver outputs the gate signals having levels which instruct the transistors of the corresponding differential pair to switch off.

Abstract: A variable delay circuit delays a carrier signal having a predetermined frequency, and outputs a modulated signal. A delay setting unit sets a delay period for the variable delay circuit according to a data signal to be modulated. The delay setting unit assigns each symbol in the data signal to any one of positive edges and negative edges in the carrier signal, and sets a delay period for the variable delay circuit at the timing at which a positive edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the positive edge. Furthermore, the delay setting unit sets a delay period for the variable delay circuit at the timing at which a negative edge in the carrier signal passes through the variable delay circuit, according to the symbol value in the data signal assigned to the negative edge.